Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection

Abstract

Abstract-Image processing for intelligent cameras like those as the one presented in this paper is to provide very fast used in video surveillance applications implies computational and efficient dynamic reconfiguration, allowing the user to demanding algorithms activated in function of non predictable extensively exploit time multiplexing over a given set of silicon events, such as the content of the image or user requests. For extesi eoitetime m exin overagie setsofs such applications, hardwired acceleration must be restricted to resources. For intellgent cameras reconfigurable processors a minimum subset of kernels, due to the increasing NREs when provide an appealing alternative. They allow intensive runapplication update become necessary. Embedded reconfigurable time re-use of the acceleration logic, properly configurated to processors, coupling in the same computing engine a general-the specific (and possibly event-driven) required task. purpose embedded processor and field-programmable fabrics,In this paper, a motion detection algorithm requiring moreprovide an appealing trade-off point between pure software and dedicated hardware acceleration. As a case-study, this than 10 different basic operation kernelis rconsidered as a paper presents the implementation of a set of image processing case-study in order to show the possibilities offered by reconoperators utilized for motion detection on the DREAM adaptive figurable computing, and to analyze the different design trade-DSP. With respect to pure software solutions, the proposed imple-offs. A key point of this work is that impressive performance mentation achieves a performance improvement of 2-3 orders of improvements with respect to a software solution (2-3 order magnitude, while retaining the same degree of programmability ofmagnitude) were achieved after (roughly) 1 month of work and the same economical perspectives from the end-user point mostly performed by an unexperienced MSc student. Many commercial SoC solutions in the field of image in order to reduce data sizes while retaining most relevant processing or wireless telecommunication (e.g. ST Nomadik, informations. In many applications, the image processing flow TI OMAP, Philips Nexperia) feature today architectures based may depend on real-time events. As an example, motion detec-on a main control processor (commonly an ARM processor), tion could activate a procedure for object/human recognition. accelarated by a constellation of dedicated circuits or AppliTraditional implementation of this kind of image processing cation Specific DSPs. From an economical perspective, this algorithms consists in utilizing standard processors as control trend is very promising also for the incoming years, and in this engines and FPGAs as programmable accelerators. In fact, scenario we propose the DREAM adaptive DSP, developed in motion detection systems normally require average-low imple-the Morpheus project timeframe [2]. The DREAM [1] adaptive mentation costs, and such an approach is acceptable only for DSP is r...

A 142MOPS/mW integrated programmable array accelerator for smart visual processing

“…Following the considerations of previous section, this section provides performance comparison of IPA running at 100 MHZ with respect to the CPU running at 45 MHZ clock frequency, that are the operating frequency of the two architectures at the operating voltage of 0.6V. The experiment is carried out on a smart visual surveillance application [7] performing on 160x120 resolution of images, consisting 9 different motion detection kernels including morphological filters (e.g. finding minimum and maximum pixel, erosion, dilatation, Sobel convolution), and a smart trigger kernel asserting an alarm if the size of the detected objects surpasses a defined threshold, the latter kernel composed of highly control intensive code.…”

An Intelligent Surveillance Platform for Large Metropolitan Areas with Dense Sensor Deployment

“…reviews in [23,31,32]). Some recent studies considered tracking performed by a network of embedded smart cameras [33,34] and specific hardware architectures [35]. Recent designs for low-energy surveillance systems include a hybrid low-resolution stereo “sensor” coupled with higher resolution color camera [36], development of light-weight algorithms for embedded smart cameras [32,37], and smart camera networks for agricultural applications [38].…”

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

“…• Image processing for intelligent cameras can be viewed as a large collection of real time algorithms, which can be activated in function of non-predictable events (such as the content of the image or a request from the user). It includes functions such as image enhancement, contour extraction, segmentation into regions, objects recognition or motion detection [4]. Typically, processing need ranges from 10 10 to 10 12 operations per second.…”

“…The application mapping on DREAM is described in [4], while here the extension to the whole MORPHEUS architecture is introduced. The application is subdivided in 5 different main kernels, described in Table 4.…”