Copper (Cu) chemical–mechanical polishing (CMP) using a multiplaten approach is a key process in the fabrication of Cu interconnects. It is customary to employ different slurries on each platen in a bid to optimize the performance of the Cu CMP process. These slurries generally contain abrasive particles that aid in the removal of material during CMP, but their presence is likely to result in the formation of scratches. In this article, a defect source analysis (DSA) technique was employed to identify the different types of scratches that were generated progressively by the three platens of an Applied Materials Mirra CMP polisher. In addition, the DSA technique also allowed tracking of the scratches from one platen to the next. Our results showed that scratches due to platen 1 were likely to result in more damage, and this was attributed to the use of alumina abrasive particles on platen 1.

No abstract

As device dimensions shrink to the sub-65 nm regime, a greater demand is placed upon the barrier polishing process. Therefore the ability to modulate the barrier chemical mechanical planarization performance window by process and formulation synergy can provide tunability at advanced technology nodes to meet stringent electrical, topography, and defect requirements. This study introduces one approach in achieving the synergy between barrier polishing slurry and the development of a robust process. The system investigated has demonstrated desirable R s uniformity control and greater margin for polishing. Extensive M x layer testing ͑more than 10 wafer lots͒ has consistently shown better within-wafer R s ͑resistance͒ spread compared to process of record, with improvement above 30% for all layers. The slurry also shows a more gradual R s fluctuation over a 20 s polish time range. A marathon run has also shown consistent polishing rate performance over the pad life with comparable defect density and characteristics.Chemical mechanical planarization ͑CMP͒ has been the key enabling technology of damascene interconnects and is now the backbone in BEOL architecture for sub-0.13 m logic chips. In damascene integration, the oxide is first etched to form via and trench patterns on the dielectric surface. A thin barrier metal is deposited followed by a thick copper film. Excess burden of copper is then removed by CMP. This integration scheme has many advantages, namely, it eliminates the etching of copper, gives global planarization essential for additional metal layers build, reduces mask layers, and reduces failures between metal lines and vias. 1 In the CMP process, planarization of metal and interconnect is achieved by polishing a wafer with uneven topology on a polymeric pad held by a rotating platen using a slurry consisting of submicrometer abrasive suspended in a chemical mixture consisting of an oxidizer, pH stabilizers, surfactants, metal-ion complexant, rate inhibitors ͑block-ers͒, and corrosion inhibitors.As device geometries shrink, new materials are introduced and film stacks become more complex. Furthermore, electrical and reliability demands become more stringent, and the drive for low defectivity becomes imperative. The barrier polishing step exemplifies this requirement perfectly, with the need to polish multistack dielectrics like SiN, NBLOK, and SiO 2 , and C-doped dielectrics like Si-COH and barrier/liner novel metals. Furthermore, as the final polishing step in the multiplaten Cu CMP process, it could potentially mask or enhance defects and create trench profiles that could impact electrical and reliability performances profoundly. Adding to the problem, different integration schemes of varying relative thicknesses of these multistacked films as well as the need to either remove or retain the protecting hard mask ensure that the barrier slurry needs to be easily tunable. There have been numerous studies in the slurry-consumable interactions, 2,3 and here we try to demonstrate a slurry formulation method...

No abstract