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Complex designs often contain voltage islands that can operate at lower supply voltages to reduce power. These circuits require multiple supply voltages, however, it is challenging to bring in and distribute several voltages on a chip. In this paper, a fully integrated DC-DC buck converter for regional power regulation is introduced. A charge-recycling scheme is used to capture some of the energy stored in the clock-tree load and feed the charge into the DC-DC converter. Furthermore, using the multi-GHz system clock for switching significantly reduces the size of the output filter components, making their integration feasible. As a proof of concept, the proposed circuit is implemented in a 1P7M2T 90nm CMOS process. It operates at 3GHz to convert an input voltage of 1.0V to an output voltage of 0.5 to 0.7V with 40 to 100mA load current.The major drawback of using a high switching frequency is that the dynamic switching loss in the circuit is increased. Directly combining the clock-tree chain with the converter switching transistors and gate driver chain merges the converter switching losses with the clock-tree switching losses. Zero-voltage switching (ZVS) and clock-tree charge-recycling are used to further reduce power loss and improve conversion efficiency. A delay circuit implemented inside the clock-tree chain provides the dead-time needed to implement ZVS. To adjust and regulate output voltage, the duty-cycle of the clock signal is changed by a control circuit. Therefore, this clock signal is intended for circuit blocks that are insensitive to clock duty-cycle, such as edge-triggered flip-flops.The idea of using an inductor inside a clock distribution network was previously used in [1], in which a clock resonance scheme reduces power loss in the clock network. In comparison, we use charge recycling and ZVS to decrease clock power loss.Figure 29.8.1 shows the block diagram of two implemented systems: a typical clock-tree network and our converter. A chain of cascaded inverters is used as a clock buffer. C clk represents the clock network capacitance. When the clock is high, C clk is charged through M p . In the other half of the clock cycle, C clk would normally be discharged to ground through M n , wasting the stored charge. Instead, M p and M n can be considered as the power transistors of a switching buck converter and recycle the clock-tree charge to the output filter and consequently to the load. Mode 1 is intended to drive the load and charge C clk through M p . During this time, inductor current increases linearly since the voltage across it is constant.Mode 2 is intended for charge recycling. Therefore, both M n and M p . are off. The charge that is stored in C clk is moved to the output circuit through the inductor. This results in a rapid drop of V clk , which is intended.Mode 3 starts when the voltage across M n is close to zero. At this time M n is turned on to provide a low-resistance path for the inductor current. As a result, inductor current decreases linearly. The ZVS operation occurs when M ...

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Abstract-Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region.