A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid

Alimadadi, M.; Sheikhaei, Samad; Lemieux, Guy; Mirabbasi, Shahriar; Dunford, W.G.; Palmer, P.R.

doi:10.1109/tcsi.2009.2037850

Cited by 5 publications

(4 citation statements)

References 24 publications

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“…Increasing the WL voltage stepwise is effective for reducing energy dissipation. As for the clock driver, a charge recycling circuit with an inductor has been proposed and its effectiveness was confirmed by experiment [17]- [20]. As for SAR (successive approximation register) analog-to-digital converters [14], it has been shown that stepwise charging is effective for reducing energy dissipation.…”

Section: Introductionmentioning

confidence: 95%

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General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Nakata

Honda

Makino

et al. 2012

IEEE Trans. Circuits Syst. I

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The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory.

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Section: Introductionmentioning

confidence: 95%

“…The voltage waveform is sinusoidal due to the resonance. For the LC nonresonant circuit, it has been reported that power consumption is reduced to 65% of the total at 4 GHz [20]. The voltage waveform is nearly square with fast edges.…”

Section: Features Of Stepwise Circuitmentioning

confidence: 99%

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Nakata

Honda

Makino

et al. 2012

IEEE Trans. Circuits Syst. I

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“…The required wide programmability is not feasible with classical analog solutions but can be achieved with digital signal processors (DSPs). Classical clocked DSPs have advanced through robust solutions but are still difficult to implement at very high clock rates, due to power requirements for clock generation and distribution [1], [2], EMI issues, and the need for an antialising filter. Further, such processors continue dissipating dynamic power even during lulls in the input, unless complex power management scenarios are adopted.…”

Section: Introductionmentioning

confidence: 99%

Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation

Kurchuk

Weltin-Wu

Morche

et al. 2012

IEEE J. Solid-State Circuits

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Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the limitations of conventional digital and analog implementations. Per-edge digital signal encoding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each consuming negligible power while awaiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm and achieves dynamic range of over 20 dB in the 0.8-3.2-GHz signal range. The system's rate of operations automatically adapts to the signal, thus causing its power dissipation to vary in the range of 1.1 to 10 mW according to input activity.Index Terms-Asynchronous processing, continuous-time (CT) digital filter, CT processing, CT digital signal processor (DSP).

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“…The solution generally adopted is that of a closed-loop-with-active-compensation that is implemented by means of phase-locked loops (PLLs) and delay-locked loops (DLLs) [12], [13]. In this context, much effort has been devoted to reducing jitter and power [4], [14]- [21]. However, these techniques are also generally power-and area-hungry.…”

mentioning

confidence: 99%

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Favi

Kluter

Mester

et al. 2012

IEEE Trans. Circuits Syst. I

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Abstract-We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical signal that is detected through a Single-Photon Avalanche Diode (SPAD) capable of timing uncertainties as low as 50 ps.The CIUs comprise a free-standing local oscillator serving a computing area of a few tens of square micrometers, thus resulting in extremely reduced power dissipations, since the distribution of a high frequency clock over long distances is avoided. This approach is based on the globally asynchronous locally synchronous concept, whereby the granularity of the local domains is reduced to a minimum, thus enabling extremely high local clock frequencies and low power, while minimizing substrate noise injection and intra-chip interference.Thanks to this approach we can free ourselves from expensive synchronization techniques such as FIFOs, delays, or ip-op based synchronizers by creating xed synchronization points in time where data can be exchanged. The paradigm is demonstrated on a chip designed and fabricated in a standard 90 nm CMOS technology. A full characterization demonstrates the suitability of the approach.Index Terms-Clock distribution, embedded systems, globally asynchronous locally synchronous (GALS), instruction set extensions (ISEs), optical clocking, optically clocked ISEs, single-photon avalanche diode (SPADs).

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A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid

Cited by 5 publications

References 24 publications

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

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