This letter describes the capacitance-voltage (C-V) characteristics of a new nonvolatile Al2O3 memory with nanoscale thin film deposited by electron-cyclotron-resonance sputtering. Al-rich Al2O3 was fabricated at a reduced oxygen gas flow rate and used as a charge storage layer of the Al2O3 memory, which is located between the tunnel insulator and blocking insulator. C-V characteristics show a large hysteresis window due to the Al-rich structure, but there is no hysteresis window in the case of stoichiometric Al2O3 structure. This memory will stay nonvolatile for several years or more. The number of electrons injected into the insulator in the case of nanoscale memory cell length is discussed. A discussion of the statistical Gaussian distribution indicates that about 50 localization sites are necessary in Al2O3 memory with 10nm cell length for realizing a 1.8V change of the threshold voltage, which corresponds to the control of ten electrons in the insulator. This structure is easily achieved by the proposed Al-rich Al2O3 memory.

An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of V T variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.

Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vth's) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vth's are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski et al. was found to be the most suitable definition for predicting the distribution and the write yield.

Abstract-An adiabatic 1-kb SRAM circuit was designed, which enables gradual charging during writing and reading while maintaining a large VDD so that the problems of V T variation and electromigration in the nanocircuit can be resolved. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that the memory cell power line is set in a high-impedance state. Then, we can write data easily by inputting adiabatic signal from one bit line, while the other bit line is set to ground. For reading, a verifying operation is proposed for resolving the electromigration problem. The word line voltage is changed stepwise while the voltages of the bit lines are verified. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and found that there is no area penalty. In addition, a new charge recycle circuit with tank capacitors is proposed.

Electron transport was studied in AlGaAs/GaAs wires fabricated using focused Ga-ion-beam implantation. Single-wire samples 0.2–10 μm wide and 20 μm long were prepared with various ion doses ranging 2×1011–4×1012 cm−2; multiple-wire samples 0.1–0.3 μm wide and 10 μm long were prepared with an ion dose of 2×1011 cm−2. Electron mobility is reduced in the narrow wires because of the implantation-induced damage, and this mobility degradation is diminished by reducing the ion dose. These behaviors are consistently explained in terms of a diffusive scattering effect inside the channel and at the sidewall of the channel. Mobility in wires with the 2×1011 cm−2 ions is predominantly determined by the sidewall specularity. A 0.2-μm-wide wire with this ion dose exhibits a mobility of 2×105 cm2/(V s) and a specularity above 0.8. These values exceed those previously reported for wires fabricated using ion implantation and probably arise from the annealing employed in the present work. Conductance steps are observed with a single 0.2-μm-wide wire, and enhanced transconductance steps occur in multiple-wire samples. These behaviors are related to mobility modulation that occurs when one-dimensional subbands cross the Fermi level.