Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

Makino, H.; Nakata, Shunji; Suzuki, Hirotsugu; Mutoh, S.; Yoshimura, Tsutomu; Iwade, Shuhei; Matsuda, Yoshihisa

doi:10.1109/tcsii.2011.2124531

Cited by 47 publications

(20 citation statements)

References 13 publications

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“…Based on the modeling proposed in [16], the variations due to Random Dopant Fluctuations (RDF), channel length variations, and/or temporal variability such as Random Telegraph Noise (RTN) and other sources of variations are modeled as: (10) This method can capture the effect of different sources of variations including process, noise and aging [16].…”

Section: A Read Snm Distributionmentioning

confidence: 99%

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Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Saeidi

Sharifkhani

Hajsadeghi

2014

IEEE Trans. Circuits Syst. I

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A fast statistical method for the analysis of the Read SNM of a 6 T SRAM cell in near/subthreshold region is proposed. The method is based on the nonlinear behavior of the cell. DIBL and body effects are thoroughly considered in the derivation of an accurate closed form solution for the Read Static Noise Margin (SNM) of the near/subthreshold SRAM cell. This method uses the state space equation to derive the Read SNM of the cell as a function of threshold voltage of cell transistors. This function shows the dependency of the Read SNM on sizing, , temperature, and threshold voltage variations. It provides a fast reliability analysis for a cell array of a given size and a supply voltage. It also calculates the accurate value of failure probability of the cell. The analytical results are verified using Monte-Carlo simulations in 45 nm Predictive Technology Models. Index Terms-Analytical modeling, data stability in SRAM, failure probability, random dopant fluctuation (RDF), subthreshold.

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Section: A Read Snm Distributionmentioning

confidence: 99%

“…The work reported in [10] assumes a linear relationship between the statistical variables and the performance metrics to estimate the failure probability of a memory. However, it does not provide closed-form expressions for the failure probability.…”

Section: Introductionmentioning

confidence: 99%

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Saeidi

Sharifkhani

Hajsadeghi

2014

IEEE Trans. Circuits Syst. I

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“…If the write margin is linear for the Vth's, it is expected to obey the normal distribution, allowing us to predict the write margin distribution accurately from a small number of samples. If the write margin distribution follows the normal distribution, the write yield can also be easily estimated [6]. The dependence of the WNM on the Vth is examined using the SPICE simulation.…”

Section: Conventional Write Noise Marginmentioning

confidence: 99%

“…While the WNM is not linear on the Vth of the access transistor N1, the WNM is almost linear on the Vth's of the other transistors. Nonlinearity on the N1 causes the WNM to deviate from the normal distribution [6]. In the lower ΔVth region, the load transistor P1 determines WNM=0.…”

Section: Conventional Write Noise Marginmentioning

confidence: 99%

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Accelerated evaluation method for the SRAM cell write margin using word line voltage shift

Makino

Nakata

Suzuki

et al. 2011

2011 International Symposium on Integrated Circuits

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An accelerated evaluation method for the SRAM cell write margin is proposed based on the conventional Write Noise Margin (WNM) definition. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is used because the access transistor operates in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The amount of WNM shift is determined from the WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. A normal distribution of the AWNM drastically improves development efficiency, because the write failure probability can be estimated by a small number of samples. Effectiveness of the proposed method is verified using the Monte Carlo simulation.

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A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

Ebrahimi

Asadpour

Afzali-Kusha

et al. 2015

Circuit Theory & Apps

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Summary In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.

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Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

Cited by 47 publications

References 13 publications

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Accelerated evaluation method for the SRAM cell write margin using word line voltage shift

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

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