Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Saeidi, Roghayeh; Sharifkhani, Mohammad; Hajsadeghi, Khosrow

doi:10.1109/tcsi.2014.2327334

Cited by 21 publications

(4 citation statements)

References 19 publications

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“…6T-SRAM performance factors are shown in Table II. [30][31][32][33] In static operations, R P causes an observable effect under both read and write conditions. On the other hand, for dynamic evaluations, dummy gates cause a minimal increase in parasitic capacitance.…”

Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

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Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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“…Due to the deviation of the device manufacturing process and external noise interference, SRAM may have reading errors [23,24,25]. When facing a large number of reading operations, the stability of the read is more important.…”

Section: Rsnmmentioning

confidence: 99%

A new reading mode based on balanced pre-charging and group decoding

Qin

Lin

et al. 2020

IEICE Electron. Express

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In this paper, the balanced pre-charging and group decoding are presented to realize in-memory computing which can achieve continuous read operations after only one pre-charge operation. Compared with the analog computing of multi-row parallel reading, this structure adopts digital domain computing, which improves the accuracy of computing; compared with the non multi-row in-memory computing, it improves the computation speed. The simulation results of noise margin, read times, and read speed show that the proposed method can improve memory performance. The maximum stability can be improved by 13.8%, the read speed can be improved by 75%, and the power consumption can be reduced by 11.58%. Besides, it can be widely used in a variety of memory structures. The proposed method is applied to the existing in-memory computing structures to verify the effectiveness.

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“…However, low supply voltage design faces challenges like high delay, temperature variation and also the circuit becomes more sensitive to radiation effect as compared to the high supply voltage 6) . A further important problem is that voltage scaling 7) , which is extensively utilized in ultralow power devices like medical devices and smart grids etc 8) , reduces the speed and stability of SRAM 9) . Meanwhile, in nano-scale CMOS technologies, with the aggressive decrement in feature size of transistor, SRAMcircuit integration has attained high density with great improvement in its performance.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Soft Error Resilient 14T SRAM Cell

Sahi,

Bharti,

Ms. Ashima Sharma

2023

Evergreen

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As part of this effort, the CC14T, cross-coupled memory cell with 14 transistor architecture has been proposed, with defence against soft errors such as single event upsets (SEUs). The CC14T cell is presented, which consists of 4 cross-coupled input-split inverters and four access transistors. The cell achieves optimum SEU tolerance owing to a feedback structure among its internal nodes. It has been implemented and analyzed under 40nm regime, and the findings demonstrate that it consumes 43.01 nW of power with supply voltage of 0.8V and takes 6.64 percent and 15.5 percent less time to write and read than a typical 6T SRAM cell. As compared to the other cell considered, the CC14T cell has a faster write access time and higher stability due to its soft error resistance.

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Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Cited by 21 publications

References 19 publications

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

A new reading mode based on balanced pre-charging and group decoding

Design and Implementation of Soft Error Resilient 14T SRAM Cell

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