Nonvolatile memory using Al2O3 film with an embedded Al-rich layer

Nakata, Shunji; Saito, Kimitoshi; Shimada, Masaru

doi:10.1063/1.2137449

Cited by 33 publications

(26 citation statements)

References 14 publications

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“…Nanoscale devices have been widely researched [1,2] for large-scale integration and low-energy operation. A 10-nm-node CMOS circuit is expected for low-energy operation.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Nakata

2006

IEICE Electron. Express

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Abstract:The simplified adiabatic SRAM is proposed which enables gradual charging during writing mode so that problems of electromigration and hot carrier effects can be resolved. For simplicity, we do not use a regenerator circuit for charge recycling in the circuit. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that we set the memory cell power line to be in a high-impedance state. Then, we input adiabatic signal from one bit line to charge the memory cell power line to V DD . This writing method enables gradual discharging and charging. As for reading, the word line voltage is decreased to V th , or it is changed stepwise while the voltages of bit lines are verified. These reading methods enable the gradual change. With the gradual charge transfer in writing and reading modes, the SRAM can avoid electromigration and hot-carrier effects even in the less-than-45-nm process, while it maintains an operating voltage of 1 V or more. Keywords: adiabatic charging, high reliability, SRAM, nanocircuit Classification: Integrated circuits References[1] S. Nakata, "Observation of Coulomb-blockade oscillations by the back gate with subattofarad mutual capacitance," Phys.

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“…Nanoscale devices have been widely researched [1,2] for large-scale integration and low-energy operation. A 10-nm-node CMOS circuit is expected for low-energy operation.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Nakata

2006

IEICE Electron. Express

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“…Next, we discuss the charge trap density in the Al-rich consistent with that in the previous consideration [7].…”

Section: Charge Trap Densitymentioning

confidence: 86%

“…We clarified that the structure is very effective for nanoscale devices due to its simple structure and thin insulator [6][7][8][9]. However, a concern for this device is the interface between the Al 2 O 3 and Si.…”

Section: Introductionmentioning

confidence: 99%

Charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films fabricated by radio-frequency magnetron co-sputtering

et al. 2011

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A thin-film structure comprising Al 2 O 3 /Al-rich Al 2 O 3 /SiO 2 was fabricated on Si substrate. We used radio-frequency magnetron co-sputtering with Al metal plates set on an Al 2 O 3 target to fabricate the Al-rich Al 2 O 3 thin film, which is used as a charge storage layer for nonvolatile Al 2 O 3 memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. , which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for lowcost nonvolatile memory.

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“…Nanoscale devices have been widely researched [1,2,3], and, particularly, the development of a 10-nm-node CMOS circuit is expected for large-scale integration and low-energy operation. However, there is a problem of the threshold voltage V th variation.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic quasi 6T-SRAM with shared writing and reading ports

Nakata

2008

IEICE Electron. Express

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An adiabatic quasi 6T-SRAM is proposed in which a memory cell shares the writing and reading ports between a flip-flop and a bit line so that the transistor number in a memory cell is decreased to about six. The gradual charging operation in the circuit can avoid electromigration and hot carrier effects. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually by using a high-resistivity nMOSFET, and the nMOSFET is turned off to set the memory cell power line in a high-impedance state. Then, adiabatic signal from the shared writing port is input to charge the memory cell power line to VDD. In the reading mode, the shared reading port, which connects the flip-flop and the bit line, is used for stable operation. The bit line can be precharged to a small value (for example, VDD/4), which enables a small current flow during the reading mode. Logic data are read by sensing the voltage decrease in the precharged bit line. Keywords: adiabatic charging, writing and reading ports, sharing, 6T-SRAM, nanocircuit Classification: Integrated circuits References[1] S. Nakata, "Observation of Coulomb-blockade oscillations by the back gate with subattofarad mutual capacitance," Phys.

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Nonvolatile memory using Al2O3 film with an embedded Al-rich layer

Cited by 33 publications

References 14 publications

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films fabricated by radio-frequency magnetron co-sputtering

Adiabatic quasi 6T-SRAM with shared writing and reading ports

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