Adiabatic quasi 6T-SRAM with shared writing and reading ports

Nakata, Shunji

doi:10.1587/elex.5.163

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…Therefore, in our design, the MCGL voltage is increased to VDD/2 to maintain data. When reading, the shared reading port is used [5]. The memory cell is connected to the local BL (LBL), which is connected to the global BL (GBL) with the shared reading port.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

Nakata

Suzuki

Honda

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of V T variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.

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Section: Introductionmentioning

confidence: 99%

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

Nakata

Suzuki

Honda

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Self Cite

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Low power SRAM using Adiabatic Logic

Varma

Sasipriya

2020

J. Phys.: Conf. Ser.

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In this paper the design of low power SRAM has been presented. SRAM memory cell has been realized using adiabatic logic to achieve low power operation. Adiabatic SRAM has been realized using two methods such as i) gradual charging and discharging of bit-line during writing mode and ii) utilizing control transistor based adiabatic circuit i.e., Two Phase Adiabatic Dynamic Logic (2PADL) circuit for the design of memory cell. Furthermore, energy recovery of word line and bit line charge stored in the interconnect capacitances has been realized for the benefit of energy savings. Charge recovery circuits based on 2PADL has been employed in the proposed SRAM memory core to achieve energy recovery. SRAM memory array of (4×4) has been designed as a test circuit. All the circuits are implemented using 180nm CMOS technology and simulations are carried out using Cadence® Virtuoso tool. Simulation results prove that the proposed memory cell has significant amount of energy savings when compared to the conventional static CMOS SRAM cell.

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Adiabatic quasi 6T-SRAM with shared writing and reading ports

Cited by 2 publications

References 8 publications

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

Low power SRAM using Adiabatic Logic

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