Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

Abstract

An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of V T variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.

Adiabatic SRAM for Low Power Devices

“…One is for designing the memory cell ground line voltage and therefore the remaining for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally [3]. Hong Li, Linfeng Li, and Jianping Hu in 2010 showed that with rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption bit by bit.…”

Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading

“…This is because 3VDD/4 can be comparatively easily generated using a tank capacitor circuit without energy dissipation [5]. In this case, VRP in Fig.…”

“…The cell size is 1.72 µm × 4.62 µm. There is no area penalty compared with the previous circuit [5].…”

“…The MCGL is shared in 16 words (row0-row15). The difference from the circuit in [5] is that only the read word line (RWL) goes high during reading, while the RWL and the write word line (WWL) go high during writing. The GBL and BL are set to the precharged voltage (VPC) using a precharged circuit.…”

“…To solve the V T variation problem in SRAM, we have proposed adiabatic SRAM that changes the memory-cell power line or memory-cell ground line (MCGL) gradually during writing [4,5]. However, there has been no detailed discussion of static noise margin (SNM) during reading between two bit lines (BLs) and a single BL as a function of the precharged BL voltage.…”