The requirements of high-throughput Internet servers necessitate the use of multiple ALUs in high-performance 64b execution cores. Consequently, each ALU demands a compact, energy-efficient 64b adder core with single-cycle latency. The resultant critical path, which is a balanced mix of interconnect, diffusion and gate loads, forms a representative test bed for evaluating competing circuit techniques and process technologies (bulk CMOS/SOI). This paper presents: (i)the design of an energy-efficient 64b ALU in 0.18µm bulk CMOS technology (ii)a direct port of this design to a comparable SOI technology and (iii)an SOI-optimal redesign of the adder core. Further, it describes design margining required for the SOI implementations and reports the results of shrinking the two architectures to 0.13µm Bulk/SOI. In both cases, a sophisticated SOI compact model that incorporates features to effectively model the SOI floating body effect is used.The 64b ALU is based on a single-rail, radix-2, Han-Carlson (HC) adder core [1] with two wide multiplexer stages and a write-back bus (Figure 20.3.1). The HC adder core performs carry-merge on alternate bit slices. Consequently, it has 50% fewer carry-merge gates when compared to a conventional Kogge-Stone adder (at the cost of an additional final carry-merge stage). The reduced active leakage (21% smaller) and an efficient energy-delay characteristic make it suitable for the 64b bulk CMOS ALU (Figure 20.3.2a).

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