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As Bluetooth V1.1 [1] compliance is achieved by several solutions, the original low power objective re-emerges as a key factor for integration in portable devices. Since the standard -70dBm sensitivity was achieved with ease, commercial solutions have converged on a worst-case -80dBm sensitivity to attain longer reach from Class-2 output power (< 4mW) devices. This paper presents the second generation of a 1.8V Bluetooth transceiver [2]. Peak current consumption is 24mA for the receiver and 18mA for the transmitter at 6dBm output power.A prerequisite for low power operation is a low voltage supply. All the RF/analog circuitry is functional down to 1.65V. The digital section is designed to work at 1.3V, despite the high threshold voltages of the 0.5µm/3V CMOS backend. Architecture selection has a large impact on transceiver power consumption. For the transmitter, two-point closed-loop direct modulation is used to generate the 2-GFSK modulated carrier. The fractional-N deltasigma (fN-DS) synthesizer required to permit various crystal reference frequencies is reused to generate the low-frequency band of the modulated signal. The high-frequency band is realized by direct analog VCO frequency modulation. The receiver uses a low-IF heterodyne architecture to allow on-chip implementation of the analog channel filters. The GFSK demodulator is implemented in the digital domain for maximum flexibility. This allows power consumption reduction through on-chip digital supply voltage regulation.The receiver chain starts with a differential LNA with inductive degeneration. The LNA output drives an RF power detector whose output is quantized to 1-bit, with 5dB of hysteresis. Quadrature mixers downconvert the RF signal to a 1MHz IF. The mixers have two gain settings 12dB apart. The mixers gain mode can be set directly by the 1-bit RF detector output, or it can be set by the receiver controller based on the combined RF and IF RSSI level.Most of the receiver gain and selectivity is provided in the analog IF strip, which alternates complex bandpass filter (CBPF) stages with variable gain amplifiers (VGA). A solution based on filtering first followed by signal limiting was rejected due to the high power consumption required by a low noise, high dynamic range and high linearity filter preceding the limiting strip. Alternating filter and gain stages allows better trade-offs between noise figure and linearity for each stage, by progressively reducing the dynamic range as the signal level is amplified. A typical IF stage is shown in Fig. 5.3.1. The CBPF stage is based on transconductor-RC circuits and has third-order intermodulation products below -60dBc when exercised with two 125mV pp tones. Filter tuning is based on RC delay measurements. A peak detector (PkD) circuit measures the power of the signal at the output of the filter stage. The PkD output is quantized to a 3-bit word that controls the 8-level VGA. During the data packet, the VGA's are operated in "hold" mode, in which the previously sampled PkD outputs are stored and applie...

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A dual-IF GPS receiver front-end integrates all the active circuitry to down-convert, amplify and digitize the 1,575.42 GHz L1 signal. The chip includes 3 dB NF LNA, 38 dB image reject mixer, VCO with integrated LC tank and varactor, PLL synthesizer, 55-dB range AGC with charge-pump control, 2-b A/D, crystal oscillator and TTL-compatible buffers. The receiver noise figure is 4 dB and maximum gain is 120 dB with a power consumption of 49 mA at 3 V supply. The AGC and 2-b AID offer better SNR and significantly better blocking performance than the commonly used 1-b quantizers.