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Decreasing the power consumption of CMOS digital circuits by both supply voltage (VB) and threshold voltage (VT) reduction (by technology) is limited by the VT spread (technology and temperature dependent). This paper presents a control circuit that minimizes the sum of the dynamic and static power consumption by reducing and controlling both the supply and threshold voltages. To compensate for temperature and technology variations, the latter is electrically adjusted by bulk biasing. The control loop has been designed such that the speed is maintained. IntroductionThe power consumption ( P ) of a CMOS digital gate equals the sum of dynamic and static power (Pdyn and P&.Assuming a mean output signal duty cycle of 50%, a total load capacitance C, a maximum frequency of operationf-, a standby current of the digital gate Io, the specific current of the MOS Zsn,p ( I s = 2npC0, -UT), the slope factor n and UT the thermal voltage, the power consumption for one gate equals:2) The activity ratio at is defined as the ratio betweeithi repetition frequency of operation f and the maximum frequency of operation f -: (3.4)Assuming the MOS always operates in saturation, the gate delay fdn,p can be approximated by:To avoid the classical discontinuity in the MOS drain current model I&,+, near Vgs=VT, we use the following model that gives an acceptable precision in a very wide range of currents [13 (NMOS):The formulas (4,5,6) show that by decreasing both VB and VT, the speed (fd can be maintained. For a large number of gates (Ng), the total power consumption Pt is :The approximation introduced by (7) uses the averaged values of gate capacitance and standby current of the gate G. With m the number of gate transition cycles to carry out an operation, the average gate activity is defined as : Minimizing Power consumptionThe goal of our circuit is to minimize the power consumption without speed loss. Figure 1 shows the power consumption of an existing microprocessor as function of the supply voltage VB. The maximum frequency is maintained for both curves by adjusting VT. The upper curve has a larger average gate activity a than the lower one. For VB lower than UT [l], no signal regeneration is possible and so digital circuits can not work. For a high VB value, the power consumption is dominated by the dynamic power. For a low VB value the static power is dominant. An minimum power consumption exists between those two regions. 1 0.5 3 0.2 E 0.1 .B 6; 0.05 0.02 Fig.1 Calculated power as function of VB for the same fmax (100MHz) with al=l%(f=lMHz) for the upper curve and a2=0.1%(100kHz) for the dashed line.Corresponding value of VT are plotted as a function of VB in fig.2. From those two figures it can be seen that the actual power consumption may increase significantly above the minimum power consumption because of a typical uncontrolled VT spread of +200mV (due to technology, temperature). Therefore, when lowering both supply and 78

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