Reducing the substrate losses of RF integrated inductors

On the design of RF spiral inductors on silicon

“…For example, it is possible to transfer the role of silicon as the mechanical substrate carrier to a glued-on glass substrate, so that all silicon outside of the active device regions can be removed [34]. Local reduction of the silicon substrate losses can be achieved through an n-well formation [35], a lateral pn doping structure [36], a thick buried oxide layer [37], the formation of porous silicon [38], [39], or proton bombardment [40]. Near elimination of the substrate losses can be accomplished by local removal of the silicon [41]- [47] or by using high-aspect-ratio and surface micromachining techniques [48]- [51].…”

On the ultimate limits of IC inductors-an RF MEMS perspective

“…In the example of Fig. 3(a) [5], this is accomplished by inserting narrow stripes of n + regions perpendicular to the current flow such as to create blocking p-n-p junctions. This blocking structure resulted in a Q improvement from 5.3 to 6.0 (13.2%) at 3.5 GHz on a 1.8nH inductor, obtaining an inductance-per-turn of 0.9nH.…”

“…In addition to being frequently employed in passive tuning circuits, or as high-impedance chokes, many novel techniques to achieve low-voltage operation in advanced silicon IC processes rely on the negligible DC voltage drop across inductors when utilized as loads or as emitter/source degenerators [3][4]. When fabricated in a planar process, the trace capacitance to ground tends to lower the inductor selfresonance frequency, and the substrate conductivity tends to lower its quality factor (Q) [5]. While optimization of the spiral geometry and line width [2], [5][6] is essential to tailor the frequency of maximum Q, this exercise only addresses minimization of the trace ohmic losses and substrate capacitance.…”

“…When fabricated in a planar process, the trace capacitance to ground tends to lower the inductor selfresonance frequency, and the substrate conductivity tends to lower its quality factor (Q) [5]. While optimization of the spiral geometry and line width [2], [5][6] is essential to tailor the frequency of maximum Q, this exercise only addresses minimization of the trace ohmic losses and substrate capacitance. Thus, a number of attempts to use conventional processing techniques to diminish the substrate losses created by eddy currents induced by the magnetic field of the spiral have been pursued.…”

“…Thus, a number of attempts to use conventional processing techniques to diminish the substrate losses created by eddy currents induced by the magnetic field of the spiral have been pursued. For instance, while [5] introduced blocking p-n-p junctions in the path of the eddy current flowing in an underlying p + layer, [7] introduced a patterned metal ground shield to also block the eddy current. These, and similar approaches, however, only achieve modest relative improvements and, certainly, do not achieve Qs much greater than 10, or self-resonance frequencies greater than a few GHz.…”