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This paper describes the development and testing of a digital radio frequency memory (DRFM) kernel, as well as some of the functionality which has been added to the system to make it a fully-fledged hardware in the loop (HIL) radar environment simulator (RES) system for radar testing and evaluation.

Developments over the past decade in technology such as high-speed analog-to-digital converters (ADC), digital-toanalog converters (DAC) and field-programmable-gate-arrays (FPGA) contributed to the simplification of the hardware design of wideband digital radio frequency memories (DRFM). The progression in FPGA technology enabled the implementation of real-time wideband digital signal processing (DSP) algorithms for test and evaluation of present-day radars.

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