The design, construction, and operational testing of a five-stage, fully interconnected 32 × 16 switching fabric by the use of smart-pixel (2, 1, 1) switching nodes are described. The arrays of switching nodes use monolithically integrated GaAs field-effect transistors, multiple-quantum-well p-i-n detectors, and self-electro-optic-device modulators. Each switching node incorporates 25 field-effect transistors and 17 p-i-n diodes to realize two differential optical receivers, the 2 × 1 node switching logic, a single-bit node control memory, and one differential optical transmitter. The five stages of node arrays are interconnected to form a two-dimensional banyan network by the use of Fourier-plane computer-generated holograms. System input and output are made by two-dimensional fiber-bundle matrices, and the system optical hardware design incorporates frequency-stabilized lasers, pupil-division beam combination, and a hybrid micro-macro lens for fiber-bundle imaging. Optomechanical packaging of the system ut lizes modular kinematic component positioning and active thermal control to enable simple rapid assembly. Two preliminary operational experiments are completed. In the first experiment, five stages are operated at 50 Mbits/s with 15 active inputs and outputs. The second experiment attempts to operate two stages of second-generation node arrays at 155 Mbits/s, with eight of the 15 active nodes functioning correctly along the straight switch-routing paths.

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A 4 x 18 two-dimensional array of GaAs FET-SEED (Field Effect Transistor-Self Electrooptic Effect Device) differential transimpedence receivers has been fabricated for application in massively parallel optical data link board-to-board interconnections. Several FET-SEED receiver arrays were tested and displayed a mean response of -0.7 mV/p W, and were capable of >lo0 Mbps per channel operation. The mean receiver sensitivity for a BER of < lo-' was calculated from the measured noise spectrum to be -26.8 dBm at the system design rate of 40 Mbps (18 k-22 MHz bandwidth), and -23.2 dBm for a 100 Mbps rate (dc-66 MHz bandwidth). A sensitivity of approximately -25 dBm for the 40 Mbps rate was confirmed using a bit-error-rate test set. The theoretical noise is compared to measured values with good agreement assuming a FET channel noise factor of 1.4. The l/f noise corner frequency of -13 MHz was found to cause a -1.2 dB degradation in sensitivity for the 100 Mhps rate. The differential amplifier mean dc output offset voltage was measured to be 10 mV, and displayed a large sigma due to parameter variations in the active devices. Two receiver arrays were successfully used in a demonstration of a fully differential parallel optical Small Computer System Interface (SCSI) data link.

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