Five-stage free-space optical switching network with field-effect transistor self-electro-optic-effect-device smart-pixel arrays

Abstract

The design, construction, and operational testing of a five-stage, fully interconnected 32 × 16 switching fabric by the use of smart-pixel (2, 1, 1) switching nodes are described. The arrays of switching nodes use monolithically integrated GaAs field-effect transistors, multiple-quantum-well p-i-n detectors, and self-electro-optic-device modulators. Each switching node incorporates 25 field-effect transistors and 17 p-i-n diodes to realize two differential optical receivers, the 2 × 1 node switching logic, a single-bit node control memory, and one differential optical transmitter. The five stages of node arrays are interconnected to form a two-dimensional banyan network by the use of Fourier-plane computer-generated holograms. System input and output are made by two-dimensional fiber-bundle matrices, and the system optical hardware design incorporates frequency-stabilized lasers, pupil-division beam combination, and a hybrid micro-macro lens for fiber-bundle imaging. Optomechanical packaging of the system ut lizes modular kinematic component positioning and active thermal control to enable simple rapid assembly. Two preliminary operational experiments are completed. In the first experiment, five stages are operated at 50 Mbits/s with 15 active inputs and outputs. The second experiment attempts to operate two stages of second-generation node arrays at 155 Mbits/s, with eight of the 15 active nodes functioning correctly along the straight switch-routing paths.

Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture

“…The physics of "LC" and "RC" lines is substantially different, but, somewhat surprisingly, the aspect ratio limit on bit-rate capacity shows the same scaling in both cases, and also in the case of equalized "LC" lines. The aspect ratio limit is approximately B ~ B o A/" 2 bits/s, with B o ~ 10 15 (bit/s) for unequalized "LC" lines, ~10 16 for "RC" lines, and ~10 17 -10 18 for equalized "LC" cables. These limits are relatively independent of the details of the design of the line because of the logarithmic scalings involved in the underlying physics (though bad design could make the limits worse).…”

“…Optics in various forms has been suggested for use in high-capacity switching systems [26] [4]. Experimental optically-interconnected multistage systems have been demonstrated [16]. The use of optics for very-high-aspect-ratio interconnections within a switching system is being researched now; in one such experimental system, a single silicon chip forms the core switching fabric interconnecting a large number of highcapacity switching machines [14].…”

Device Requirements for Optical Interconnects to Silicon Chips

“…For example, a 6 stage system with over 60,000 light beams was demonstrated using such free-space optics [106]. Some earlier work focused on optical interconnected optoelectronic logic device arrays [99]- [101], and later work has investigated CMOS chips with large arrays of optoelectronic devices hybrid attached to the chips [107], [108]. Much of this work used quantum well diode structures exploiting the strong quantum-confined Stark effect electroabsorption [109] to make the optoelectronic logic or modulator devices.…”

Toward an optimal foundation architecture for optoelectronic computing Part I Regularly interconnected device planes

“…98 Not only is knowledge of the mathematical aspects well developed, 97 but also optical implementations in the form of switching networks have been demonstrated. 99,100 What we have argued is that such systems are reasonably close to the best possible as defined by physical limitations.…”