In deep sub-micron (DSM) technology, crosstalk noise and logic faults caused due to shrinking wire-size and reduced inter-wire spacing are major factors affecting the performance of on-chip interconnects such as high power consumption and increased delay. In this paper, a novel spatio-temporal bus encoding scheme to minimize the crosstalk in interconnects is proposed that simultaneously addresses error detection requirement also. The proposed scheme eliminates crosstalk classes 4, 5 and 6 among the interconnect wires, thereby reducing delay and energy consumption. Also, the proposed scheme has the feature of built-in error detection without any performance overhead. The effectiveness of the proposed technique is evaluated by focusing on L1 cache address/data bus of a microprocessor using SPEC2000 CINT benchmark suites for 90nm and 65nm technologies. The proposed technique achieves an efficiency of 11% in energy consumption and a reduction of about 33% to 63% in delay when compared to the base case for data transmission and is shown to perform better than the existing bus encoding schemes in literature.

Field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiationinduced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.