A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection

Abstract

In deep sub-micron (DSM) technology, crosstalk noise and logic faults caused due to shrinking wire-size and reduced inter-wire spacing are major factors affecting the performance of on-chip interconnects such as high power consumption and increased delay. In this paper, a novel spatio-temporal bus encoding scheme to minimize the crosstalk in interconnects is proposed that simultaneously addresses error detection requirement also. The proposed scheme eliminates crosstalk classes 4, 5 and 6 among the interconnect wires, thereby reducing delay and energy consumption. Also, the proposed scheme has the feature of built-in error detection without any performance overhead. The effectiveness of the proposed technique is evaluated by focusing on L1 cache address/data bus of a microprocessor using SPEC2000 CINT benchmark suites for 90nm and 65nm technologies. The proposed technique achieves an efficiency of 11% in energy consumption and a reduction of about 33% to 63% in delay when compared to the base case for data transmission and is shown to perform better than the existing bus encoding schemes in literature.