Effect of slot plane antenna (SPA) Ar plasma on the reliability of intermediate plasma (DSDS) treated ALD Hf1-xZrxO2 samples with x = 0, 0.31, 0.8 were investigated. The metal oxide semiconductor capacitors (MOSCAP) were subjected to a constant field stress of 27.5 MV/cm in the gate injection mode and the stress-induced flatband voltage shifts and stress induced leakage currents were monitored. The dielectric film deposited without any intermediate step (As-Dep), having the same number of atomic layer deposition (ALD) cycles as DSDS samples was used as the control sample. It was observed that plasma exposure enhances the quality of high-κ film by reducing the number of intrinsic traps in the film and Zr addition further enhances the reliability. Breakdown characteristics also confirm this behavior. Electron affinity variation in HfO2 and ZrO2 and Zr variation seems to contribute to the improvement in DSDS Hf1-xZrxO2 (x = 0.8) by suppressing the oxide trap formation as observed in the Weibull characteristics. DSDS Hf1-xZrxO2 with x = 0.8, therefore, demonstrates a superior equivalent oxide thickness (EOT) downscaling ability and good reliability performance.

This work has demonstrated a high quality HfO2 based gate stack by depositing atomic layer deposited (ALD) HfAlOx along with HfO2 in a layered structure. In order to get multifold enhancement of the gate stack quality both Al percentage and distribution were observed by varying the HfAlOx layer thickness and it was found that < 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in average EOT along with up to six fold reduction in gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increased the interface state density (Dit). When devices were stressed in the gate injection mode at a constant field stress dielectrics with Al/(Hf+Al)% ~ 2% showed resistance to stress induced flat-band voltage shift (DVFB), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics of these devices showed a reduced charge to breakdown and an increase in the extracted Weibull slope (β) that further confirms an enhanced dielectric reliability.

In this work, the dry and wet processed interface layers for three different p type Ge/atomic layer deposition (ALD) 1 nm-Al2O3/ALD 3.5 nm-ZrO2/ALD TiN gate stacks on 300 mm wafers were studied at low temperatures by capacitance–voltage (CV), conductance–voltage measurement, and deep level transient spectroscopy. The interface treatments were (1) simple chemical oxidation (Chemox); (2) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR and SPAOx); and (3) COR followed by vapor O3 treatment (COR and O3). Since low temperature measurements are more reliable, several parameters like equivalent oxide thickness, flatband voltage, bulk doping, and surface potential as a function of gate voltage are reported. Different temperature CV measurement suggests that all the samples are pinned at flat band voltage (Cit give a pseudoaccumulation region) due to large Dit (larger than 1013 cm−2/eV). Room temperature measurement indicates that superior results were observed for slot-plane-plasma-oxidation processed samples.

The reliability of atomic layer deposited Hf1-xZrxO2 with x=0.8 on a SiON interfacial layer (IL) has been analyzed in detail for three different oxide deposition processes, (i) DADA: samples were subjected to dielectric deposition and thermal annealing in a cyclical process; (ii) DSDS: samples were subjected to similar cyclical process with dielectric deposition and exposure to Ar plasma; and (iii) As-Dep: the dielectric for the control samples was deposited without any intermediate step. Capacitance-voltage and current-voltage characteristics of the MOS capacitors (MOSCAP) with metal gate (TiN), subjected to a constant field stress of 2.75 × 107 V/cm in the gate injection mode, show that the flat-band voltage shift (∆VFB ) and stress induced leakage current (SILC) below 100 s stress is the lowest for DSDS samples whereas the worst degradation was observed for DADA samples. However, identical degradation was observed in all sample types when stress was increased to 1000 s. Intermediate plasma exposure (DSDS process) seems to supress the oxide trap formation as it provides EOT downscaling ability and good reliability performance. The reliability characteristics, when compared with pure HfO2, seem to improve with the addition of ZrO2.

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (&lt;3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ∼ 0.2 eV modify to V2+ type to Ea ∼ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ∼0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.