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This paper presents an approach for high-quality builtin test using a neighborhood pattern generator (NPGJ. Proposed NPG is practically acceptable because ( a ) its structure is independent of circuit under test, (b) it requires low area overhead and no performunce degradation, and (c) it can encode deterministic test cubes, not only for stuck-at faults but also transition faults, with high probability. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

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This paper presents a BIST approach for the very deep submicron (VDSM) defects in ASIC. As bridging or open defects are dominant in VDSM, efficient and accurate tests to detect them are now strongly required. We evaluated the BIST patterns in various criteria. These evaluations and additional real chip experiments have indicated that the BIST has better detectability of defects than the conventional stored test.