A BIST approach for very deep sub-micron (VDSM) defects

Logic BIST is well known as an effective method for low cost testing. However, it is difficult to realize at-speed testing, as it requires a deliberate timing design in regard to logic design and layout of the chip. This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme. Some experimental test results of large industrial designs using our custom tool "Singen", will also be shown.

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“…Their frequencies are ordinary from 30MHz to 500MHz. The DFT is constructed of logic BIST, memory BIST and the boundary-scan [10]- [15].…”

Section: 2mentioning

confidence: 99%

DFT timing design methodology for at-speed BIST

Suzuki

Sato

Kawashima

et al. 2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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“…(2) [4]. In this equation, G denotes the number of gates and α denotes a numerical value from 0.5 to 1.5, which is determined empirically.…”

Section: Introductionmentioning

confidence: 99%

Test point insertion methods to reduce the number of ATPG patterns

Yoshimura

Hosokawa

Ohta

2006

Electron. Comm. Jpn. Pt. II

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SUMMARYThe increasing density of LSI chip circuits is causing the execution time of tests based on the full-scan design method to become problematical. In this paper, the authors propose a method of reducing the number of ATPG patterns for a full-scan designed LSI chip by inserting test points. To reduce the number of ATPG patterns, they proposed a test point insertion algorithm based on the improved fault detection probability and a test point insertion algorithm based on the improved value assignment probability. When the authors applied the proposed methods to several actual LSI chips, they were able to reduce the number of ATPG patterns by 48% to 78% compared with the conventional full-scan design by adding test points equivalent to 0.4% to 2.2% of the total number of flip-flops in the LSI chip.

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“…This merit enables to use low cost tester and results in the reduction of total test cost [2]. Another reason is high fault coverage for various fault models or even for unmodeled faults [3]. Though this advantage, which is caused by the large number of test patterns, may increase test application time, several techniques, such as the use of large number of scan chains and the acceleration of scan-shift cycle, can overcome this demerit.…”

Section: Introductionmentioning

confidence: 99%

Application of high-quality built-in test to industrial designs

Hatayama

Nakao

Kiyoshige

et al.

Proceedings. International Test Conference

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This paper presents an approach for high-quality builtin test using a neighborhood pattern generator (NPGJ. Proposed NPG is practically acceptable because ( a ) its structure is independent of circuit under test, (b) it requires low area overhead and no performunce degradation, and (c) it can encode deterministic test cubes, not only for stuck-at faults but also transition faults, with high probability. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

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A BIST approach for very deep sub-micron (VDSM) defects

Cited by 12 publications

References 18 publications

DFT timing design methodology for at-speed BIST

DFT timing design methodology for at-speed BIST

Test point insertion methods to reduce the number of ATPG patterns

Application of high-quality built-in test to industrial designs

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