In this article, the impact of several electrical and technological parameters on a particular type of Lorentzian noise, occurring in deep submicron silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors with an ultrathin gate dielectric is described and a semi-empirical model is proposed that captures the main features of the experimental behavior. It is shown that the noise takes place in both n- and p-channel partially depleted SOI transistors. The excess Lorentzians are also found in the n-channel fully depleted devices studied, whereby the noise plateau amplitude [SI(0)] increases for a more negative back-gate bias, putting the back interface into stronger accumulation. The dependence of the characteristic time constant τ and SI(0) on transistor length, drain, front- and back-gate bias is reported, where from a first-order model is derived. The latter is based on the idea that the excess Lorentzian noise originates from filtered shot noise induced by majority carriers, that are injected in the floating body of the transistors by electron valence-band tunneling across the ultrathin (2.5 nm) gate oxide.

This work describes the low-frequency noise of forward biased shallow p-n junctions fabricated in epitaxial silicon substrates. Particular emphasis is on the effect of silicidation on the low-frequency noise spectral density . It will be demonstrated that the observed 1 noise is significantly larger in Co-silicided junctions compared with the nonsilicided ones. A detailed analysis of the current and geometry dependence of leads to the conclusion that the 1 noise is of the generation-recombination (GR) type, with the responsible GR centres homogeneously distributed over the device area. From the correlation with the forward current-voltage (I-V) characteristics, it is derived that GR fluctuations in the hole current through the + region cause the increased 1 noise in the silicided devices.

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The nature of the non-trivial low-frequency (LF) current noise of both generation-recombination (GR) and 1/f type observed in accumulation and depletion mode (AM/DM) p-MOSFETs and enhancement mode (EM) n-MOSFETs fabricated in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) substrates is investigated, for gate biasing conditions where either the front or the back p-Si/SiO 2 interface is in weak or strong inversion. The noise considered increases sharply with increasing positive gate voltage near the inversion threshold and is very high under strong inversion conditions.For the GR noise, it has been shown that both the noise relaxation time τ and the spectral density S I (0) at the low frequency plateau of the corresponding Lorentzians are only determined by the inverting front (back) voltage U Gf,b in AM/DM p-MOSFETs, while the drain current is the main factor determining τ and S I (0) in EM n-MOSFETs. As to the 1/f noise, a high scatter in the data obtained in different samples has been observed in SOS DM p-MOSFETs and a correlation between the level of this noise and the behaviour of the current has been revealed. Arguments are presented that the GR and 1/f noise at stake are of a similar physical nature and are typical for devices with an inverted p-Si/SiO 2 interface. It is shown that the responsible noise centres are located in a narrow layer of the p-type silicon film in the close vicinity of the p-Si/SiO 2 interface. A model to explain all non-trivial features of both the noise and the current is proposed and validated.

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