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Adaptive background updating is one of the methods used to detect moving objects in video sequences. Many techniques have been presented in this field but there are few mentions about the usage of these methods in real-time applications. We concentrate in the speed of the algorithm and present a method that is fast enough to be used in video surveillance systems. We started from the ideas presented by Gaussian distribution for background generation. Instead of using actively all the pixels in the image we divide the pixels into active and inactive ones. Gaussian distributions are used to model the history of active pixels and to state whether they belong to background or foreground. According to the classification of the previous active pixel also the inactive pixels are classified as a part of the background or foreground. We also reduce the frame frequency and use only every n th frame in the image sequence to construct adaptive background. This article is organised as follows: In Chapter 1 some of the previous work and their results are introduced. In Chapter 2 we first describe the method used by Stauffer and Grimson [3] and then present our new ideas. The results are explained in Chapter 3 and finally a conclusion is given.

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This document describes an innovative approach for simulating a DSP processor with VLIW architecture, the simulator structure and shows a performance comparison with a state of the arts simulation tool. The simulation approach is based on a threedimensional (phase, time, operation) representation of the pipeline in order to "grab" in a certain time stamp the complete processor status, taking into account the current status and the following. This approach allows to accurately simulate the C6x behavior reducing the simulation time compared with the others on-market available simulators. Moreover the VLIW simulator generating dynamically the instruction set is a flexible tool for the hardware-software co-design.

In this paper an optimized implementation of the HEVC video decoder is shown. The solutions developed to support the new features of HEVC are shown together with the achieved performance. The HEVC decoder complexity has been evaluated and the most demanding modules have been optimized exploiting SIMD instructions. Even though the here described concepts have a general value, the effectiveness of the proposed solutions has been verified on the ARM architecture. The selected architecture is ARM Cortex A9 with NEON SIMD extension. We will demonstrate that the resulting real-time HEVC software decoder can decode 720p (1280x720) streams at 30 frames per second on a single core ARMv7 at 1.2 GHz.