In FFT algorithms memory access patterns prevent multiple architectures from achieving high machine use, particularly when parallel processing is needed to achieve the desired efficiency rates. Beginning with the extremely powerful FFT heart, the on-chip memory hierarchy for the multicored FFT processor, is co-designed and linked on-chip. We have shown that the Floating Processing Factor (FPPE) proposed achieves greater operating rate and lower power for the application of health informatics. This test mechanism aids in omission of faulty cores and autonomous detection also makes elegant multi-core architecture degradation feasible. Experimental results illustrate that the anticipated design is scalable widely in terms of performance overhead and hardware overhead which makes it appropriate to many-cores with more than a thousand processing cores through Low Power and High Speed.