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In FFT algorithms memory access patterns prevent multiple architectures from achieving high machine use, particularly when parallel processing is needed to achieve the desired efficiency rates. Beginning with the extremely powerful FFT heart, the on-chip memory hierarchy for the multicored FFT processor, is co-designed and linked on-chip. We have shown that the Floating Processing Factor (FPPE) proposed achieves greater operating rate and lower power for the application of health informatics. This test mechanism aids in omission of faulty cores and autonomous detection also makes elegant multi-core architecture degradation feasible. Experimental results illustrate that the anticipated design is scalable widely in terms of performance overhead and hardware overhead which makes it appropriate to many-cores with more than a thousand processing cores through Low Power and High Speed.

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Now a days VLSI application speed and area reduction is very important one. In this paper implemented AES algorithm.AES represents an algorithm for advance encryption standard of different operation required in the steps of encryption and decryption. The proposed architecture is based on optimizing area in terms of reducing and improve throughput for design of AES algorithm in VHDL .this paper presents AES-128 bit algorithm design consist of 128 bit symmetric key and XILINX ISE 14.1 project used for synthesis and simulation of this proposed design