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In short-channel CMOS devices with extension structures, current crowding was found to occur in the source extension, significantly degrading current drivability. Reducing this effect by using high-dose extensions and low parasitic capacitance provided by a localized punchthrough stopper layer produced high drivability, enabling a sub-10-ps CMOS gate delay to be attained.

Analyzing charge retention characteristics, we found that a flash memory with a critical tunnel oxide thickness has the cells with anomalous threshold-voltage (Vth) lowering. We proposed the model that the traps near the poly-Si gatdtunnel oxide interface generate anomalous leakage current in the voltage range of 0 -1 V, and the lrappingldetrapping of electrons into the lraps dominates Vth distribution. We succeeded in suppressing the anomalous leakage current of a tunnel oxide by fluorine implantation into a Si substrate.

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