Two Dimensionally Inhomogeneous Structure at Gate Electrode/Gate Insulator Interface Causing Fowler-Nordheim Current Deviation in Nonvolatile Memory

Ushiyama, M.; Ohji, Yuzuru; Nishimoto, Toshiaki; Komori, Kazuhiro; Murakoshi, H.; Kume, Haruki; Tachi, Shinichi

doi:10.1109/irps.1991.363254

Cited by 5 publications

(3 citation statements)

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“…The floating gate deposition step significantly affects the tunneling characteristics: doping dose, annealing temperature and doping species play important roles [33]. In fact, it has been observed that voltage deviations dramatically increase with the tunneling area reduction (see Fig.…”

Section: Ultrafast Bitsmentioning

confidence: 99%

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Reliability of erasing operation in NOR-Flash memories

Chimenton

Olivo

2005

Microelectronics Reliability

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Section: Ultrafast Bitsmentioning

confidence: 99%

“…Phosphorous segregated in grain boundaries diffuses in the oxide and forms phosphorous rich oxide which is assumed to cause oxide ridges. The use of Arsenic instead of phosphorous, as well as the reduction of annealing temperature/time and doping dose can improve the interface quality [33] and reduce voltage deviations.…”

Section: Ultrafast Bitsmentioning

confidence: 99%

Reliability of erasing operation in NOR-Flash memories

Chimenton

Olivo

2005

Microelectronics Reliability

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“…In this approach, to obtain the tight distribution of threshold voltage, pre-program for all bytes is carried out, and the gradual erase and verify sequence will be iterated until the threshold voltages for all bytes in the array are less than or equal to the desired value. Another approach is to reduce the oxide-ridge on the SiO, surface by reducing the phosphorus in the floating gate and lowering the annealing temperature after forming the floating gate [7].…”

Section: Introductionmentioning

confidence: 99%

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Yamada

Suzuki²,

Obi³

et al.

International Electron Devices Meeting 1991 [Technical Digest]

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A new erasing method for a simple stacked gate Flash EEPROMs is described. The method makes use of avalanche hot carrier injection after erasure by Fowler-Nordheimv-N) tunneling. The threshold voltages converge to a certain "steady-state" as a result of the injection. The steady-state is caused by a balance between the avalanche hot electron injection into the floating gate and the avalanche hot hole injection into the floating gate, and can be controlled easily by the channel doping. Tight distribution of threshold voltages and stable erasure without over-erased cells are demonstrated by applying cells using 0.6pm CMOS technology. In addition, short erase time is realized using the new erase sequence.

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Downscaling of floating‐gate EEPROM modules for ASIC applications

Shiba

Kubota

1992

Electron Comm Jpn Pt II

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Downscaling methods of electrically erasable programmable ROM (EEPROM) for application‐specific integrated circuit (ASIC) applications based on the double‐poly floating‐gate process were studied. Simple scaling of ASIC and EEPROM modules with the same scaling factor can significantly reduce the time for design and development. Horizontal scaling of the memory cell with unchanged vertical dimensions does not alter the cell performance because the capacitance coupling ratios are kept constant. Vertical scaling, which further reduces the cell size due to less short channel effects, requires the improvement in the tunnel oxide quality. For this purpose, an improved process also was studied in terms of process temperature and phosphorus concentration in polysilicon gate.

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Two Dimensionally Inhomogeneous Structure at Gate Electrode/Gate Insulator Interface Causing Fowler-Nordheim Current Deviation in Nonvolatile Memory

Cited by 5 publications

References 0 publications

Reliability of erasing operation in NOR-Flash memories

Reliability of erasing operation in NOR-Flash memories

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Downscaling of floating‐gate EEPROM modules for ASIC applications

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