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As the size of transistor is decreasing, more number of functionalities are integrated onto a single chip, so the interconnect length is ever increasing. Signal rise time is decreasing as compared to the time of flight. Hence, the interconnect can no longer be modelled as RC tree, rather it must be modelled as a transmission line by taking the inductance into account. With the increase in frequency, the dynamic power dissipation associated with interconnect is also increasing. Hence, an efficient method to estimate the interconnect power dissipation is necessary. In this paper, a simple yet accurate method has been proposed to estimate dynamic power dissipation of on-chip interconnect. A reduced order model is derived. The proposed model is directly derived from total resistance, inductance and capacitance of interconnects. Through the analysis made in this paper, it is shown that the dynamic power dissipation for the interconnects can be accurately estimated. The results of the proposed method applied to various RLC networks show that maximum relative error is within 4 to 6% compared to the SPICE results.

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