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In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ⩽20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

Various aspects of ultra-thin chip technology for flexible electronics are presented and discussed, including ultra thin-chip fabrication, mechanical and electrical characterization, as well as chip assembly and imbedding. A stress sensor based on a stack of two ultra-thin, flexible CMOS chips indicates the particular advantages of the ChipfilmTM process technology, which is subject of this paper, when compared to other kinds of thin-chip fabrication.

Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required.Ultra-thin Si chips (6 to 20 ȝm) are fabricated by using a recently introduced technology based on the pre/post-process modules Chipfilm™ and PickCrack&Place™ combined with a standard CMOS process. Prior to CMOS processing 200nm cavities are formed beneath the chip surface. The silicon quality is very comparable to that of bulk control wafers leading to similar process parameters and parameter variations.Fully operational digital and mixed-signal circuits having 30k and 38k/2.7k digital/analog CMOS transistors, respectively, are built on ultra-thin silicon chips by using an in-house CMOS gate array technology.The issue of piezoresistive effects in MOS transistors is studied on test transistors and small test circuits, where mechanical stress was introduced by bending a system of chip mounted on 50-μm Kapton foil. The results are compared to bulk silicon measurements. In addition, effects to circuit design, particularly on parametric yield, are deduced.The Chipfilm™ technology not only offers ultra-thin CMOS chips for electronic foil systems but can also be exploited for 3D circuit integration.

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