Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

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In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ⩽20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

Abstract-This paper analyses the bending-induced stress effects on ultra-thin cross-shaped magnetic sensors operating in voltage-or current-modes. Both the magnetic sensor's sensitivity and the offset drift have been analysed. The optimum geometry and thickness of the Hall sensor are the important parameters to be analysed to compensate any mechanical stress related effect on the performance of sensors. Numerical simulations are carried out using the finite element method (FEM) with COMSOL Multiphysics software. A compact model is implemented in Verilog-A and used for the simulations in Cadence c Spectre, considering a 350 nm CMOS process. The simulation results focus on magnetic sensor's sensitivity variation and offset drift induced by bending of the substrate. The simulation results show a sensitivity of 71 V/AT at 100 mT. Interestingly, the sensitivity variation induced by 250 MPa applied uniaxial stress is less than 0.02 %.

Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required.Ultra-thin Si chips (6 to 20 ȝm) are fabricated by using a recently introduced technology based on the pre/post-process modules Chipfilm™ and PickCrack&Place™ combined with a standard CMOS process. Prior to CMOS processing 200nm cavities are formed beneath the chip surface. The silicon quality is very comparable to that of bulk control wafers leading to similar process parameters and parameter variations.Fully operational digital and mixed-signal circuits having 30k and 38k/2.7k digital/analog CMOS transistors, respectively, are built on ultra-thin silicon chips by using an in-house CMOS gate array technology.The issue of piezoresistive effects in MOS transistors is studied on test transistors and small test circuits, where mechanical stress was introduced by bending a system of chip mounted on 50-μm Kapton foil. The results are compared to bulk silicon measurements. In addition, effects to circuit design, particularly on parametric yield, are deduced.The Chipfilm™ technology not only offers ultra-thin CMOS chips for electronic foil systems but can also be exploited for 3D circuit integration.