In this paper LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL Input

Frequency Scaling based energy efficient MBCCS is implemented in this paper. In this design, if battery's voltage or current is less than threshold then battery will continue charging. Whereas, if voltage or current is more than threshold then it will ring Overcharge Alarm. With Frequency Scaling, we reduce frequency from 1THz to 25GHz, where 125GHz, 625GHz are intermediate frequency value. There is 97.50%, 100%, 97.54%, 97.48%, 20%, 96.48 % reduction in clock power (CP), logic power (LP), signal power (SP), IOs power (IOP), leakage power and total power dissipation respectively when we scale down frequency from 1 THz to 25GHz.

In this paper we have introduced a new approach called Clock Gating and Voltage Scaling (CGVS), which is the combination of two existing techniques i.e. Clock gating and Voltage Scaling. Our aim is to design a low power Devnagari Unicode Checker (DUC) using CGVS technique. This design is implemented on Kintex-7 FPGA families, XC7K70T device, -3 speed grade and FBG676 package. From our analysis, it is observed that, with the use of clock gated technique in our target circuit and with the scaling of voltage from 1.0V to 0.1V, we are achieving clock power reduction of 98.98% on 10GHz and 1THz operating frequencies. Under same voltage scaling scheme, there is 6.66%, 10.38%, 10.64% and 10.62% less reduction in IO power, when the target circuit is operating on 1GHz, 10GHz, 100GHz and 1THz operating frequencies.

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