The main purpose of this paper is to achieve as low as possible leakage current (I OFF) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths L eff , gate stacks, gate contact materials, and gatesidewall spacers (L sp). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length L sp and L HK is investigated to get low leakage current keeping I ON /I OFF as high as possible. Moreover, the effective channel length in subthreshold conduction (L eff) is maintained greater than the gate length (L g) and the threshold voltage (V th) is adjusted by the proper metal gate work function. The performance of the proposed n-and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted I OFF is 17 pA/µ m for n-FinFET and 14.7 pA/µm for p-FinFET which are the lowest leakage currents found in recent publications. The achieved I ON /I OFF ratio for both proposed devices is found to be 12.3 × 10 6 and 11 × 10 6 , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of L sp = 10 nm and L HK = 5 nm. In addition, the short channel effects variations with L HK have been investigated. INDEX TERMS 7 nm Bulk FinFET, leakage current, SymD-k spacer, TCAD, ultra-low power.

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