Impact of process variability on FinFET 6T SRAM cells for physical unclonable functions (PUFs)

Faragalla, Mohamed; Ewais, M. A.; Ragai, Hani; Badran, Mahmoud S.; Issa, Hanady H.

doi:10.1109/icces.2017.8275272

Cited by 3 publications

(1 citation statement)

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“…Roelke et al [9] studied the impact of negative bias temperature instability (NBTI) on the cell skew. In the context of FinFET SRAM PUF stability, Faragalla et al [10] analyzed the impact of V TH variation and power supply on PSNM using simulations for 16 nm technology node. To accurately characterize the PSNM, many Monte Carlo simulations are required to model the process variations properly.…”

Section: Modeling Static Noise Margin For Finfet Based Sram Pufsmentioning

confidence: 99%

Modeling Static Noise Margin for FinFET based SRAM PUFs

Masoumian

Selimis

Maes

et al. 2020

2020 IEEE European Test Symposium (ETS)

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In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE simulations. In our experiments, we analyze the impact of process variation, technology, and temperature on the PSNM. The results show that the analytical model matches very well with the simulation model. From the experiments we conclude the following: (1) nFET variations have a larger impact on the PSNM than pFET (1.5% higher PSNM in nFET variations than pFET variations at 25°C), (2) high performance SRAM cells are more skewed (1.3% higher PSNM) (3) the reproducibility increases with smaller technology nodes (0.8% PSNM increase from 20 to 14 nm) (4) increasing the temperature from-10°C to 120°C leads to a PSNM change of approximately 1.0% for an extreme nFET channel length.

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Section: Modeling Static Noise Margin For Finfet Based Sram Pufsmentioning

confidence: 99%