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A framework for evaluating the performance of asynchronous systems is presented. Due to the dependencies among highly concurrent events performance evaluation of asynchronous circuits is a challenging process. The presented performance model is a Probabilistic Timed Petri-Net (PTPN) with possible choice places to capture the conditional behavior of the system. The proposed framework takes advantage of both static and dynamic analysis to provide precisely enough results in an acceptable time. No data manipulation is done during the simulation phase of the performance evaluation method which leads to very fast simulation. Our proposed performance estimation scheme is faster than usual post-synthesis simulation by an order of 10, while the estimated performance resides in a boundary of 3% of the total imprecision.

Single Event Upsets will gain more importance for future nanoscale architectures, which will be more sensitive to such effects. Especially for domains like space applications robust redundany methodologies are needed to make use of these new architectures. In this paper we study fine grain redundancy methodologies which can be used to construct high robust designs. Our basic approach is to localize the fault tolerance structure to a fine grain view. We then show two methodologies which are suitable for FPGAs. The methodologies are similar to Triple Modular Redundancy (TMR) which is a widely used approach for mitigating upsets and failures. However for new device generations simply replicating complete systems in TMR manner may not be sufficient anymore especially in harsh environments, such as space applications. We integrate both approaches into standard FPGA tool flows thereby introducing redundancy automatically without user interaction.