This article presents a new approach to fast mixed-mode simulation of phase-locked loops (PLLs) in time domain using Spice-like simulators and behavioral Verilog-A baseband (BB) models of voltage-controlled oscillators (VCO) and frequency dividers (FD). Other PLL blocks like phase-frequency detectors (PFD), charge pumps (CP), and loop filters (LP) can be transistor level and/or behavioral models. The use of both VCO and FD BB models in mixed-mode test bench allows fast PLL simulation and optimization of modern sophisticated PFD and CP blocks on transistor level with speedups of about 2-3 orders of magnitude

Current trend is to increase the overall use of electronic systems in daily life. Exemplarily, the complexity of automotive Electronic Control Unit (ECU) systems is rising due to the number of components involved and the tighter interactions between these heterogeneous components (analog, digital hardware or software), resulting in a more and more challenging verification. In this paper, we show that the Universal Verification Methodology (UVM), initially developed for digital systems, can successfully be extended to analog and mixed signal systems. We introduce the UVM-SystemC-AMS framework for functional verification based on SystemC and its AMS extension SystemC-AMS. Using two automotive case studies we demonstrate the flexibility of our approach both for simulation based verification and lab based validation using a Hardware In the Loop (HIL) system.

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