Fast mixed-mode PLL simulation using behavioral baseband models of voltage-controlled oscillators and frequency dividers

Harasymiv, Ihor; Dietrich, Manfred; Knöchel, Uwe

doi:10.1109/sm2acd.2010.5672294

Cited by 5 publications

(6 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The authors also adopted the linear VCO model which may be sufficient for performing verification on fixed designs, but is overoptimistic for design exploration since the VCO linearity condition is not always valid. The VCO behavioral models developed in [42,43] used lookup-tables (LUTs) inside Verilog-A modules. LUTs only hold a limited number of simulated sample points.…”

Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

View full text Add to dashboard Cite

Electronic circuit behavioral models built with hardware description/modeling languages such as Verilog-AMS for system-level simulations are typically functional models. They do not capture the physical design (layout) information of the target design. Thus, their applications are limited to early design feasibility studies and/or pre-layout functional verification. Numerous iterations of post-layout design adjustments are usually required to ensure that design specifications are met with the presence of layout parasitics. In this paper a paradigm shift of the current trend is presented that integrates layout-level information (with full parasitics) in Verilog-AMS through metamodels such that systemlevel simulation of a mixed-signal circuit/system is realistic and as accurate as true parasitic netlist simulation. The simulations performed with these parasitic-aware models can be used to estimate system performance without layout iterations. We call this new form of Verilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 as it is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design space exploration. The PLL simulation employing quadratic metamodels achieves approximately 10× speedup compared to that employing the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power dissipation are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout-accurate but fast simulation and design space exploration. The proposed method also allows much shorter design verification and optimization to meet stringent time-to-market requirements. In the PLL optimization case study, 46 % PLL power reduction was achieved using a differential evolution algorithm and the proposed layout-accurate behavioral model. Compared to the optimization using the layout netlist, the runtime using the behavioral model is reduced by 88.9 %. To the best of the authors' knowledge this is the first approach that brings layout-level accuracy to system-level design exploration and is applied towards mixed-signal design exploration.

show abstract

Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

View full text Add to dashboard Cite

show abstract

“…Clearly, the method is not unique, but it has to minimize the phase errors between transistor-level's and macromodel's simulations, which in turn determines the accuracy of locking time estimation for a large sweep of the reference signal's frequency, as well as power consumption at PLL's SST and during transient. Besides, the PWL approach was presented in [22] together with the use of a phase macromodel for VCO and divider, extracting locking time estimations, but neither power consumption nor noise figures are obtained. The PWL approximation was also used in [23], but with assumptions on the type of phase/frequency detector and loop filter.…”

Section: A Noise-free Analysismentioning

confidence: 99%

Fast and Accurate Time-Domain Simulations of Integer-N PLLs

Luca

Bolcato

Larcheveque

et al. 2017

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-We present a methodology to simulate industrial integer-N phase-locked loops (PLLs) at a verification level, as accurate as and faster than transistor-level simulation. The accuracy is measured on the PLL factors of interest, i.e., locking time, power consumption, phase noise and jitter (period and long-term). The speedup factor tends to the division ratio N for device-noise simulations. We develop a unifying technique which is able to deal with both noise-free and device-noise analyses, taking into account nonlinear and second-order effects visible at transistor-level simulation only, whereas previous works focused on one of the two analyses, separately. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for the voltage-controlled oscillator (VCO) together with the loop divider (the phase model is called VCODIV), whilst the other PLL's blocks remain at transistor level. The macromodel's phase law is characterized by a piecewise linear curve, representing the sensitivity of the VCODIV output's phase deviation with respect to the voltage variation of the VCO's control pin, and by the effects of all the VCO's and divider's noise sources on the model's output. We show two experiments on industrial PLLs, and provide guidelines for designers which highlight the steps needed to implement the methodology by using well-known analyses in circuit simulation and Verilog-A for the creation of the macromodel.

show abstract

“…The authors also adopted the linear VCO model which may be sufficient for performing verification on fixed designs, but is not useful for design exploration since the VCO linearity condition is not always valid. The VCO behavioral models developed in [1] and [6] use a tablelookup approach inside Verilog-A modules, which is not efficient for global design space exploration. An event-driven analog modeling approach was proposed in [13] which used the Verilog-AMS wreal data type to improve the model efficiency.…”

Section: Related Prior Researchmentioning

confidence: 99%

Verilog-AMS-PAM

Geng

Mohanty

Kougianos

et al. 2012

Proceedings of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with full parasitics) in Verilog-AMS through polynomial metamodels such that system-level simulation of a mixedsignal circuit/system is realistic and as accurate as the true parasitic netlist simulation. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design exploration. Based on a quadratic polynomial metamodel, the PLL simulation achieves approximately a 10× speedup compared to the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power consumption are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout accurate but fast simulation and design space exploration.

show abstract

Fast mixed-mode PLL simulation using behavioral baseband models of voltage-controlled oscillators and frequency dividers

Cited by 5 publications

References 11 publications

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Fast and Accurate Time-Domain Simulations of Integer-N PLLs

Verilog-AMS-PAM

Contact Info

Product

Resources

About