Abstract-This paper presents the design of three static RAM cells, designed to be radiation hard. The memory cells are designed with three different approaches and layout styles. Three memory arrays, each of them made with a different cell, were designed and simulated to optimize the transistor sizes. The layout of the cells has been drawn, and parasitic elements were extracted to analyze their impact on circuit performance. Simulation results demonstrate that the three cells are functional in all worst case corners. The sensitivity of each cell to single events has been estimated using a fault injection technique. A silicon prototype employing the first cell has been fabricated and characterized.