Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in failures and non-deterministic timing behavior. The effects of these phenomena are not always well understood by designers and researchers in this area.

There is increasing interest in using m-of-n delay insensitive codes for robust asynchronous global commu nication, to support the design of coding-efficient and low power channels. However, afundamental obstacle in using these codes has been complex and expensive hardware sup port. This paper addresses this issue, introducing and eval uating practical completion detector units for 2-0f-n codes. Designs are proposed for both return-to-zero (RZ) and non return-to-zero (NRZ) codes. The RZ designs build on prior work of Piestrak [14J; this paper proposes a small modi fication to their work to provide a fully timing-robust (i. e. quasi-delay insensitive, or QDI) version. The main contri bution of the paper is an efficient completion for NRZ 2-0f-n codes. Both detector architectures are modular and simple, composed of basic cells in a binary tree. Initial simula tion results were performed on several implementations of a 2-0f-9 detector using Cadence's Spectre environment, after mapping to a 90nm standard cell library. The new RZ de tector has 35% area reduction and comparable delays and energy to the earlier Piestrak design, but unlike the latter, ensures robust QDI operation. The new NRZ detector is shown to have negligible stabilization time between succes sive codewords (0.05-0.19 ns) when compared to a recent alternative approach.

Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced by metastability, even in the case where sufficient time is left for resolution. This paper analyzes the causes why Razor-based circuits fail and proposes a new scheme combining the Razor principle with stoppable clocks in a GALS setting. This scheme avoids any timing failure due to metastability and does not require any checkpointing or pipeline restarting logic, other than the usual auxiliary latch to store valid data. The experiments show how the Razor principle can be extended to any generic logic circuit, and not just to microprocessors with sophisticated pipeline flush/recovery mechanisms. In this way, the performance/power benefits of Razor can be adopted without the complex architectural changes required by the various Razor schemes in the literature. Index Terms-Digital circuits, high speed integrated circuits, low power design.1549-8328

A new delay-insensitive (DI) data encoding protocol for asynchronous global communication is proposed. It is an M-of-N Non-Return-to-Zero (NRZ) protocol and it is levelencoded, meaning that the decoding process simply uses the values of the codeword not their transitions. It has significant power and throughput benefits with respect to Return-to-Zero (RZ) codes, since no return-to-zero-phase is required. The proposed protocol also has a better (or equal) coding efficiency and it requires a similar decoding hardware as existing 1-of-N level-encoded NRZ codes (i.e., 1-of-2 LEDR and 1-of-N LETS), while it has worse (or equal) coding efficiency but requires significantly smaller decoding hardware than existing M-of-N transition-encoded NRZ codes. In particular, the 2-of-7 code, which encodes 4 data bits, completely dominates all other known DI NRZ codes since it has equal coding and power efficiency but less hardware overhead than transition-encoded ones, and it has equal power efficiency and hardware overhead but better coding efficiency than LETS.