SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits

Cannizzaro, Marco; Beer, Salomon; Cortadella, Jordi; Ginosar, Ran; Lavagno, Luciano

doi:10.1109/tcsi.2014.2365878

Cited by 17 publications

(2 citation statements)

References 14 publications

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“…In addition, considering the meta-stability of the timing elements [29,30], a TD's output pulse width T H should be greater than the sum of the setup time for the critical endpoint and hold time for the connected SEL:…”

Section: Error Detection Circuit (Edc) Conceptmentioning

confidence: 99%

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

Yu,

Li,

Deng

et al. 2023

Sensors

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This paper presents an innovative approach for predicting timing errors tailored to near-/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustable window prior to the root clock’s rising edge. By dynamically adapting the prediction window and supply voltage based on error detection outcomes, the approach effectively mitigates false predictions—an essential concern in low-voltage prediction techniques. The efficacy of this strategy is demonstrated through its implementation in a near-/sub-threshold 32-bit microprocessor system. The approach incurs only a modest 6.84% area overhead attributed to well-engineered lightweight design methodologies. Furthermore, with the integration of clock gating, the system functions seamlessly across a voltage range of 0.4 V–1.2 V (5–100 MHz), effectively catering to adaptive energy efficiency. Empirical results highlight the potential of the proposed strategy, achieving a significant 46.95% energy reduction at the Minimum Energy Point (MEP, 15 MHz) compared to signoff margins. Additionally, a 19.75% energy decrease is observed compared to the zero-margin operation, demonstrating successful realization of negative margins.

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Section: Error Detection Circuit (Edc) Conceptmentioning

confidence: 99%

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

Yu,

Li,

Deng

et al. 2023

Sensors

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show abstract

“…Therefore, EDACs must be carefully designed to avoid the timing error detector metastable. A good example to solve this problem is the SafeRazor, which is metastability robust [33]. Flip-flop is a typical cell, which can easily be made metastable when toggling its input data simultaneously with the clock sampling edge.…”

Section: B Htd Designmentioning

confidence: 99%

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Shan

Dai

Wan³

et al. 2020

IEEE J. Solid-State Circuits

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Resilient circuits based on in situ timing monitoring adaptive voltage-frequency scaling (AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) variations but suffer from 50% throughput loss during error recovery when operating at a half frequency. We propose a bi-directional adaptive clocking circuit to provide fine frequency tuning with zero latency for AVFS system. It can either stretch the clock cycle when there are timing errors to ensure correct function or compress the cycle when there are excess timing margins. To support a wide frequency range, we generate multiple phase clocks based on two delay lines and select one appropriate phase clock to obtain a stretched output clock, where balanced clock paths are obtained by a time-to-digital converter and dynamic-OR gates. Applied to a wide-operating-range AVFS system of an SHA-256 accelerator with transition detector (TD) latches, the whole AVFS system is able to respond to errors in one clock cycle, with dynamic-OR gates collecting all the errors in half a cycle and adaptive clocking circuit stretching at the current cycle. Fabricated in 28-nm CMOS, chip measurement shows that it achieves 38.6%-69.4% power gains at near threshold while reducing throughput loss during error recovery.

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Error Detection and Correction

Reyserhove¹,

Dehaene

2019

Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors

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SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits

Cited by 17 publications

References 14 publications

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Error Detection and Correction

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