We present a procedure for the characterization and the linearization of the photoresist response to UV exposure for application to the gray-scale fabrication of diffractive optical elements. A simple and reliable model is presented as part of the characterization procedure. Application to the fabrication of surface-relief diffractive optical elements is presented, and theoretical predictions are shown to agree well with experiments.

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As processor speeds enter the Gigahertz regime, the disparity between processing time and memory access time plays an increasingly important role in the overall limitation of processor performance. Furthermore, as the components continue to shrink in size, the limitations in interconnect density and bandwidth serve to exacerbate communication bottlenecks. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. Our system is monolithically fabricated on a single host substrate and preserves the VLSI-scale of integration by using meso-scopic diffractive optical elements (DOEs) for beam fan-out and signal distribution at the chip level. This architecture can alleviate the disparity between processor speeds and memory access times in addition to increasing the interconnect density and throughput by several orders of magnitude as compared to electrical interconnects. In this report, we demonstrate an optoelectronic multi-chip module (OE-MCM) that distributes the output beam from a single vertical cavity surface emitting laser (VCSEL) to approximately 35 spots with excellent spot-to-spot uniformity. The OE-MCM represents our significant progress toward building a prototype system that consists of laser drivers, VCSELs, diffractive optical elements, photodetectors and trans-impedance amplifiers integrated on a single host substrate.

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