Effects of interfaces and thermal annealing on the electrical performance of the SiO 2 /Si 3 N 4 /Al 2 O 3 ͑ONA͒ stacks in nonvolatile memory devices were investigated. The results demonstrated the principal role of Si 3 N 4 /Al 2 O 3 and Al 2 O 3 /metal-gate interfaces in controlling charge retention properties of memory cells. Memory devices that employ both electron and hole trappings were fabricated using a controlled oxidation of nitride surface prior to the Al 2 O 3 growth, a high-temperature annealing of the ONA stack in the N 2 +O 2 atmosphere, and a metal gate electrode having a high work function ͑Pt͒. These devices exhibited electrical performance superior to that of their existing SiO 2 /Si 3 N 4 / SiO 2 analogs.

Articles you may be interested inStudy of strain fields caused by crystallization of boron doped amorphous silicon using scanning transmission electron microscopy convergent beam electron diffraction method Compositional analysis of ultrathin silicon oxynitride gate dielectrics by quantitative electron energy loss spectroscopy Appl.

The structure and chemistry of silicon oxide-nitride-oxide ͑ONO͒ stacks on silicon with differently processed top oxide layers were analyzed using high-resolution transmission electron microscopy, electron energy loss spectroscopy, secondary ion mass spectroscopy, and X-ray specular reflectometry. The changes observed in the structure and chemistry of the ONO stacks were correlated with the electrical performance of these stacks in flash-memory devices. The results demonstrated that using larger thermal budgets to form the top oxide layer yields ͑i͒ broader N distribution across the nitride/oxide interfaces, (ii) reduced H content at the Si/SiO 2 interfaces, (iii) increased density of the top oxide layer, and ultimately, (iv) improved electrical performance of ONO-based memory devices.Silicon oxide-nitride-oxide amorphous multilayers ͑ONO stacks͒ attract considerable interest as the charge-storage media in nonvolatile memory devices. 1,2 Ultrathin ONO stacks are commonly prepared by thermal growth of a SiO 2 layer ͑bottom oxide͒ on silicon, followed by low-pressure chemical vapor deposition ͑LPCVD͒ of Si 3 N 4 . Subsequently, the top oxide is either grown by the nitride reoxidation or deposited by LPCVD. The typical thickness of individual layers in the ONO stacks ranges from 5 to 15 nm. The critical structural and compositional parameters that affect electrical performance of the ONO-based devices include the physical density of the amorphous oxide/nitride layers and the depth distributions of the oxygen, nitrogen, and hydrogen atoms. Few systematic studies that analyze the effect of processing conditions on these parameters in stacked ONO structures have been reported. 3-6 Some of these studies observed ONO stacks to consist of well-defined layers of SiO 2 and Si 3 N 4 3,4 with no significant nitrogen content in the oxide layers. Other studies 5,6 revealed considerable concentration of nitrogen in the top oxide layer of the ONO stacks, as well as the segregation of nitrogen to the bottom SiO 2 /Si interface. Reports of artifacts associated with nitrogen segregation to the SiO 2 /Si interface during spectroscopic measurements 7,8 added to the confusion in the interpretation of the existing data. The optimal ͑from the electrical performance point of view͒ nitrogen profile in the bottom oxide of ONO stacks remains a subject of debate. 9,10 At present, incomplete understanding of the processing-structure/chemistry-properties relations impedes rational optimization of the processing parameters for the ONO stacks. The present work is aimed at a systematic study of these relations in the ONO stacks for flash-memory applications. We applied both spatially resolved electron energy loss spectroscopy ͑EELS͒ in a transmission electron microscope ͑TEM͒ and secondary ion mass spectroscopy ͑SIMS͒ to analyze elemental distributions in the differently processed ONO stacks, while the densities of individual layers in these stacks were determined using X-ray specular reflectometry ͑XRR͒. The results of structural/compositional an...

A simple constitutive model was used to predict the efficiency of the aluminum forcefill process. The constitutive description—adopted from the one developed for bulk material—was implemented in a finite-element code and applied to simulate the forcefill process. The results are summarized in the form of a “forcefill map” showing isochrones (constant via filling time lines) on the pressure–temperature plane. Using such a diagram, it is possible to identify the process conditions that warrant complete via filling within a specified time. Comparison of the simulation results with experimental data demonstrates a semiquantitative agreement.

High dissolution rates (Ͼ5 m/min) of both n-and p-type silicon ͑͗100͒͘ were obtained by a novel process of wet silicon etching utilizing cathodic bias. This etching process results in very smooth silicon surfaces. Unlike custom wet etching, conducted in strong alkaline or in hydrofluoric acid solutions, this method is performed even in neutral solutions. A possible mechanism for Si negative potential dissolution in alkaline solutions is discussed.The development of reliable and reasonably priced processes in the fabrication of three-dimensional structures from silicon wafers, such as, micromechanical sensors, actuators, and trenches, are of great importance in the electronic industry. Electrochemical machining is a most effective technique in precise fabrications. It offers several advantages over other etching techniques. In particular, it allows the etching rate to be carefully varied and monitored during the process. In addition, it requires relatively low-cost equipment. However, the advantages of electrochemical machining have been fully exploited only for metals, while silicon electrochemical machining is less effective. Electrochemical machining is usually associated with anodic bias ͑or anodic polarization͒ performed by shifting the electrode potential in the positive direction. Acceleration in the etching rate at anodic bias occurs only if a treated material can be actively dissolved. The wider the potential range of the active dissolution, the higher the etching rate that can be achieved. Active dissolution of silicon, over a wide range of potentials, occurs only in highly corrosive and hazardous hydrofluoric acid solutions ͑HF͒. 1 In HF-free aqueous solutions, silicon is either totally passive, or actively dissolves within a narrow potential range 2,3 without the ability to regulate the etching rate. Thus, silicon is usually etched in these solutions at the open-circuit potential ͑OCP͒, since the anodic bias is largely ineffective.In this work we used cathodic bias ͑or cathodic polarization͒ as a tool in silicon electrochemical machining. Cathodic polarization is traditionally associated with a decrease in dissolution rate, immunity of materials, and protection against corrosion. Nevertheless, the acceleration of dissolution rate under cathodic polarization has been experimentally observed in metals, such as Pb, Sn, Al, Bi, Ni, and Pt. 4 -7 The effect of cathodic polarization on silicon etching was not practically examined until now. Glembocki 3 and Seidel 8 reported on a decrease in silicon etching rate under cathodic polarization. However, these investigations were carried out at potential limit of Ϫ5 V vs. a saturated calomel electrode ͑SCE͒ only. Our previous work demonstrated the ability to texture silicon under negative polarization ͑more negative potentials than Ϫ5 V). 9,10 This study shows that very high etching rates may be achieved by cathodic polarization of silicon. A possible mechanism responsible for this phenomenon is also discussed. ExperimentalCathodic etching of n-and p-type silicon ͑...