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Complexity of integrated circuits has led to millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of 10 faults per billion, which requires test structures with huge chains of 1 million or more contacts and vias. At the same time, contacts and vias are getting smaller, and thus their resistance is increasing for every new technology node. Consequently, the resistance of such chains becomes impossible to measure. To overcome this limit without increasing the number of measurement pads, we are proposing a passive multiplexer array of via chains, which breaks up a huge contact-via chain in many individually measurable subchains. Accuracy of fail rates will be increased since the fail rate can be determined based on many subchains, instead of being determined based on only one huge chain. Furthermore, this test structure better supports failure analysis since it is faster to locate a faulty contact or via. No additional devices or process steps are required which allows implementation as short flows for fast process problem debugging.

Detailed investigations and process characterizations were performed to identify and resolve the source for programmed cell charge loss and data retention capability within the EPROM cells of our 0.35 pm Non-Volatile Memory process technology. Both front and hackend processing steps influenced the data retention behavior, with the most significant impact arising fiom the use of a high density plasma(HDP) oxide as the inter-metal dielectric. We postulate that cumulative charge buildup during processing lead to the severe charge retention effects observed and near zero yield at wafer probe.

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