Abstract-This paper proposes a low complexity, high speed, regular and flexible architecture for VLSI implementation of Reed Solomon decoder. With this architecture the error locator and error evaluator polynomials of the decoder can be computed in parallel and the same datapath can be reused to realize a partially pipelined parallel RS decoder. By architecture reuse the number of required resources for the RS decoder can be adjusted to a specific application, while maintaining internal parallel computation of each RS procedure. The resulting architecture contains one type of program element, which simplifies test and fabrication.

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PurposeIn this research work, brief quantum-dot cellular automata (QCA) concepts are discussed through arithmetic and logic units. This work is most useful for nanoelectronic applications, VLSI industry mainly depends on this type of fault-tolerant QCA based arithmetic logic unit (ALU) design. The ALU design is mainly depending on set instructions and rules; these are maintained through low-power ultra-functional tricks only possible with QCA-based reversible arithmetic and logic unit for nanoelectronics. The main objective of this investigation is to design an ultra-low power and ultra-high-speed ALU design with QCA technology. The following QCA method has been implemented through reversible logic.Design/methodology/approachQCA logic is the main and critical condition for realizing NANO-scale design that delivers considerably fast integrate module, effective performable computation and is less energy efficiency at the nano-scale (QCA). Processors need an ALU in order to process and calculate data. Fault-resistant ALU in QCA technology utilizing reverse logic is the primary objective of this study. There are now two sections, i.e. reversible ALU (RAU), logical (LAU) and arithmetical (RAU).FindingsA reversible 2 × 1 multiplexer based on the Fredkin gate (FRG) was developed to allow users to choose between arithmetic and logical operations. QCA full adders are also implemented to improve arithmetic operations' performance. The ALU is built using reversible logic gates that are fault-tolerant.Originality/valueIn contrast to earlier research, the suggested reversible multilayered ALU with reversible QCA operation is imported. The 8- and 16-bit ALU, as well as logical unit functioning, is designed through fewer gates, constant inputs and outputs. This implementation is designed on the Mentor Graphics QCA tool and verifies all functionalities.

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