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A systematic approach to CMOS Low Noise Amplifier design is presented. This approach uses an input impedance matching technique based on LC Ladder filters which will provide suitable input matching in any arbitrary band (S11<-10dB), also S22 is about -10 dB in average. Using cascode structure, maximum power gain about 25 dB is achievable. Noise level is less than 3 dB over the full band of UWB. Power dissipation of this amplifier is only 8.5 mw and operates with 0.85 v supply voltage while 0.13 µm CMOS technology is used

This paper studies the electrostatic discharge effects on solar arrays in different orbits. This paper starts with a statistical overview of solar array failures and their relations with ESD events. Then the space environmental conditions and their impacts on ESD occurrence are discussed for the most commonly used orbits for satellite missions. Spacecraft charging phenomena and different modes of charging are studied further in the paper. Finally the effects of ESD events on the elements and subassemblies of solar arrays are investigated.

In this work a systematic approach is presented for an allover design of full band UWB power amplifier. Purposed approach is included in three main steps, which are CMOS amplifier core stage bias design, input matching network and output matching network design, respectively. The first step starts by considering a cascode stage which can obtain power consumption and gain conditions through mentioned equations. Second and third stages are done through designing wide band LC networks for obtaining bandwidth requirements of UWB. For show performance of presented approach, we have designed a UWB PA through these steps. Simulation results show the performance of this design procedure.