This paper aims at the total design of synchronizing clock phase quality in a master‐slave synchronization network and studies the clock path phase errors. In master‐slave synchronization, reference clock distribution paths are a major source of phase errors. It is useful to examine the phase errors using Time Interval Error (TIE), specified in units of time. In this paper, the TIE of clock paths containing multiplexers, digital transmission lines and digital synchronous terminals is analyzed. Then measurements taken for multiplexers are presented by varying a stuffing ratio. Field data taken for a 7‐link clock path, the longest effective link path in Japan, shows that in practice a TIE of less than 100 ns over a 102 – 103 s measurement period is measured, which agrees well with theoretical data.

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We describe the technology platform of AccessNova, an advanced communications project to develop high speed networks and to promote the early use of broadband applications in Chile, as the initial step in the implementation of this research and development program. In its first stage (1995-1996), this project has been a joint effort of the University of Chile and the Nippon Telegraph and Telephone Corporation (NTT). In its second stage (1997-1999), AccessNova will be expanded to include other national and international organizations as well.

In the Japanese master‐slave synchronization network, the introduction of the cesium atomic beam frequency standard as the master office oscillator for improving the frequency accuracy, and the introduction of a loosely coupled synchronization network using the digital processing type phase‐locked oscillator to improve the clock reliability, are scheduled. An analysis is made of the clock phase behavior of a multi‐link digital clock supply in the steady state. The influence on the clock phase variation by transmission line jitter and DCS (digital clock supply) temperature dependence is considered. The results are expressed by two‐sample variance ßy2(±) which shows short‐term frequency stability, and then by time interval error (TIE) which shows phase fluctuation in the time domain. The results obtained from numerical calculation give maximum TIE of the distributed clock in the domestic 9‐linked DCS (about 25 μs) and a permissible synchronization network within three links for international digital connections by comparison with the TIE recommended by CCITT.

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