AhstradWe have developed a complete single&@ GPS &ver using 0.18~11 CMOS to mzl sevaal important requhements, such as small size, low power, low m and,h& Sensitivity for mobile GPS apphtions. Tnis is the first case in which a radio has been successfuUy comhii with a baseband p " r , such as Soc., in a GPS receiver. Ihe GPS chq, with a t o t a l size of 6.4x6.4q contains a 2.3x2.G" radio part, including RF fmnt e 4 P a , IF functions, and 5ooK gates of baseband logic, including mask ROM, SRAM and Dual Port SRAM[l]. It's fabricated using 0.18-um CMOS Technology with a MIM option and ope" fmm a 1.6 to 2. C-V power supply. Experk& results show a v q low power consumpfion os typically, 57mW for a fuUy fundod chip including baseband and a high sensitivity of -1SOdBm llmugh comunameasures for subsbate coupling noise fmm the digital the high sensitivdy was successfully achieved without any extanal LNA.

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We developed a 12-bits resolver to digital converter with a new architecture. The proposed complex twin PLL architecture tracks a mechanical angle offset by the carrier frequency, i.e. � o t � � (t) . Phase detectors using Pseudo Sine-wave Generation, Offset Tracking, and Complex Domain PLL avoid complicated functions as sine/cosine ROM, ADC/DAC, up-down counter and bidirectional VCO. This LSI was fabricated in Bi-CMOS technology with 0.6-�m bipolar / 1.4-�m CMOS, and consumes 34-mA from 5-V power supply.

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