This paper presents four compact lumped-element Wilkinson power combiners (WPC) operating at 5 GHz in 28-nm bulk CMOS. To minimize the chip area, the inductances in the designs are implemented using mutually coupled coils. Two designs use star inverting coupled coils (SICC), while the other two employ delta noninverting coupled coils (DNICC). One of the two SICC-based designs (and similarly for the DNICC-based designs) incorporates a second harmonic (2f 0 ) trap to lower the total harmonic distortion and reduce the required inductances by 25%, further reducing the circuits footprint. A design methodology for effectively exploiting the mutual coupling and nullifying the coupling parasitics is presented. The coupling parasitic in the DNICC-based design is exploited to provide the WPC isolation resistance, resulting in a lumped-element WPC requiring only three components: a coupled coil and two capacitors. The measurement and simulation results are presented to confirm the theory validity. The SICC-based WPC with an area of 0.13 mm 2 achieved input return losses (RL) >17.5 dB, output RL > 11.8 dB, isolation >11.2 dB, and insertion losses (IL) <1.5 dB across 3.5-5.4-GHz frequency range. Its variant with a 2f 0 trap achieved, from 3.5-5.35 GHz, input RL >18.2 dB, output RL >11.6 dB, isolation >11 dB, IL <1.4 dB, and peak 2f 0 rejection of 18 dB at 10.2 GHz in an area of 0.13 mm 2 .The DNICC-based WPC with an area of 0.11 mm 2 achieved input RL and isolation >10 dB, output RL >15.3 dB, and IL <1.2 dB across 4.1-5.45-GHz frequency range. Its variant with a 2f 0 trap achieved, from 4.3-5.3 GHz, input RL and isolation >10.1 dB, output RL >14.6, IL <1.2 dB, and peak 2f 0 rejection of 23 dB at 10.4 GHz in an area of 0.09 mm 2 .

Abstract-The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and -F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 51% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to -47.6 dBc and -79.3 dBc, respectively.

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A novel lumped-element Wilkinson power combiner designed at 5 GHz on a 28 nm bulk CMOS process is presented. The core circuit requires only three components with two additional capacitors used to implement a second harmonic trap, further reducing the circuit area and output distortion. The circuit uses a single coupled coil to provide two series inductances used in the combiner. Additionally, the coil parasitics provide the isolation resistance, removing the need for a discrete resistor. Design equations and methodology for the coupled coil are given along with integrated circuit (IC) measurement results. Return losses (RL) and isolation are greater than 10.1 dB from 4.3 GHz to 5.3 GHz with the insertion loss (IL) lower than 1.2 dB. The active circuit dimensions are 261 µm x 346 µm giving an area of 0.09 mm 2 .

This paper presents a 5.6 GHz Class-DE power amplifier (PA) with reduced voltage stress compared to classical PA designs. CMOS PAs are susceptible to a number of breakdown phenomena such as drain oxide breakdown and hot-carrier injection (HCI) which can significantly reduce their lifespan. The Class-DE amplifier is a hard-switching device which minimizes voltage-current overlap across the channel which significantly reduces the risk of HCI effects. The PA does not use an RF choke which limits the peak drain voltage to VDD, limiting the risk of drain oxide breakdown. The driver circuit gives a duty cycle below 50% and ensures that each transistor is almost completely off before the other has turned on. The PA achieves 47.9% power-added efficiency, 22.2 dBm output power, and 28.2 dB gain with a single 2.2 V supply voltage. Transient simulations of the PA's drain currents and voltages confirm the low currentvoltage overlap which shows that the PA has much less risk of HCI effects than classical PA designs.