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This paper is NOT THE PUBLISHED VERSION; but the author's final, peer-reviewed manuscript. The published version may be accessed by following the link in th citation below.

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This paper presents a speed-optimized large area avalanche photodetector (APD) in standard CMOS technology for visible light communication applications (VLC). Recent research efforts have reported high speed CMOS APDs with low breakdown voltage for considerably small photodiode sizes, which limits the APD usage in low cost optical receivers for VLC. The speed of a large-area APD dramatically decreases due to increased transit time of diffusive carriers in charge neutral regions. The proposed technique divides the active area into multiple subsections to decrease transit time and increase speed. A prototype 350×350 µm 2 APD is fabricated in 0.13-µm CMOS technology. The photodetector achieves a maximum gain of 7.6 K at 11 V reverse bias, showing excellent agreement with simulation results as calculated using the nonlocal impact ionization model based on recursive dead-space multiplication theory (DSMT). 2-D device level simulations validate the speed enhancement by comparing the small signal simulation results of three P+/N-well photodiodes with the same area detector composed of different number of sub-sections.

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