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Power dissipation during testing is substantially higher than during normal operations due to increased switching activity. Test vector ordering is an effective method to reduce switching activity in combinational circuits and scan chain reordering has been often cited as an effective technique for reducing power dissipation in the scan chain during testing. This paper describes a techniquefor re-ordering of test vectors and scan cells to minimize power dissipation in full scan combinational circuits during test application. The reduction is achieved by decreasing the switching activity and spurious transitions between consequent test vectors and scan cells. We formulate the test vector and scan reordering problem as a travel salesman problem (TSP) using hamming distance between test vectors and scan cells. One of the successful approaches to solve TSP is using genetic algorithm (GA) and we use standard genetic algorithm to solve this problem. Experiments performed on the ISCAS-85 and ISCAS-89 benchmark suite show a reduction in power test applying (41] for s298) as well as a reduction in power test vector inserting (25o for s298).

The ever-growing complexity of the modern chips is forcing fundamental changes in the way systems are designed. System-on-a-Programmable-Chip (SOPC) concept is bringing a major revolution in the design of integrated circuits, due to the fact that it makes unprecedented levels of in-field integration possible. Genetic Algorithm (GA) is a powerful function optimizer that is used successfully to solve problems in many different disciplines. A major drawback of GA is that it needs huge computation time for sequential execution on PCs. Therefore, the hardware implementation of GA has been the focus of some recent studies. Parallel GA (PGA) is particularly important for efficient hardware implementation and promise substantial gains in performance and results. In this paper, a SOPC-based PGA framework is proposed. Our proposed framework can be used in real-time applications. We have implemented our proposed system on an Altera ® Stratix Development Kit and we compare its performance with the corresponding software simulation. The results obtained indicate a speedup of up to 50 times in the elapsed computation time.

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Morphological filters are an important class of small portions of the signal, where again the size and shape nonlinear signal/image processing and analysis tools. These of the SE dictate which characteristics of the signal get filters have been successfully used in a wide range of removed. A thorough discussion of the operations can be applications. Designing this kind of filters needs a prior found in [1] and [2]. Further examples of morphological knowledge in mathematical morphology. Genetic algorithm operations, library structuring elements, and the process of is an automatic approach to design of these filters which generating filters are described in [13].needs little prior knowledge. In this paper, we propose some heuristics to improve the designed filters such as integerThe need to explore and experiment with different representation instead of binary representation in combinations of operations, structuring elements, and chromosomes, using four operators instead of the parameters makes the task of designing morphological conventional two, and using two structural elements instead filters well suited for evolutionary search.of one. Experimental results with some examples in noise reduction tasks are shown. Existing analytical design methods for morphological filters are computationally intractable and require expert knowledge in mathematical theory of morphology.